Tuesday 29 September 2015

CloudNet 2015 call for participation (Niagara Falls, Canada)





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4th IEEE International Conference on Cloud Networking (CloudNet 2015)
5-7 October 2015 // Niagara Falls, Canada // http://www.ieee-cloudnet.org/
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Click here to register http://www.ieee-cloudnet.org/registration.html

The organizing committee is delighted to invite you to the 4th IEEE International Conference on Cloud Networking (CloudNet 2015) to be held in Niagara Falls, Canada, 5-7 October 2015.  
CloudNet 2015 will feature keynotes, technical sessions, posters, demonstrations, and a panel session addressing the key theme of Cloud Networking.

TECHNICAL PROGRAM

The technical program of CloudNet 2015 is focused on aspects related to Cloud and Datacenter networks. It offers several types of sessions including technical, poster, demo and panel sessions covering a variety of topics such as Inter and Intra Cloud networking, Datacenter network architectures and services, Datacenter network management, Cloud federation, Mobile Cloud computing, Cloud network virtualization and energy efficiency in Datacenter networks.

More details about the program on http://www.ieee-cloudnet.org/program.html


KEYNOTE SPEAKERS

- Albert Greenberg (Partner Development Manager, Microsoft)
- Thierry Coupaye (Head of research on cloud platforms, Orange Labs)
- Prof. Nelson Luis Saldanha da Fonseca (University of Campinas, Brazil)

More details about the keynotes on http://www.ieee-cloudnet.org/keynotes.html

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VISITOR INFORMATION

The conference will be held in beautiful Niagara Falls http://www.niagarafallstourism.com
Full Fallsview suites can be booked at the conference hotel using CloudNet conference page 

More details to organize your venue on http://www.ieee-cloudnet.org/travel.html

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Conference Chair
Raouf Boutaba, University of Waterloo, Canada

Technical Program Committee co-Chairs
Noura Limam, University of Waterloo, Canada
Burak Kantarci, Clarkson University, USA

Steering Committee
Raouf Boutaba, University of Waterloo, Canada
Guy Pujolle, University Pierre & Marie Curie, France
Deep Medhi, University of Missouri - Kansas City, USA
Dzmitry Kliazovich, University of Luxembourg, Luxembourg
Puneet Sharma, HP Labs, USA

More info at: http://www.ieee-cloudnet.org/

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Call for Poster and Demo: IEEE GreenCom 2015 (Green Computing and Communications)





Call for Poster and Demo:

The 11th IEEE International Conference on Green Computing and Communications (GreenCom 2015), 11-13 Dec. 2015, Sydney, Australia.

Website: http://www.swinflow.org/confs/greencom2015/demo.htm

Key dates:
Deadline for proceedings published posters/demos: 5 October 2015
Notification of Acceptance: 8 October 2015
Final versions of proceeding published posters/demos: 15 October 2015
   
Submission
Please email your posters/demos to confs.aus@gmail.com with the email subject as "GreenCom 2015 poster demo submission".
     
Two types of posters and demos:
1. Proceedings published posters and demos: Submission is a 2-page short
paper describing the post/demo content, research, relevance and importance
to Internet of Things or related topics. If accepted, the 2-page short
paper will be published in the main conference proceedings together with
regular research papers. Each accepted poster or demo must register to the
main conference with full registration.
     
2. Web published posters and demos: Submission is a 1-page extended
abstract. Such posters/demos will not be included in the conference
proceedings, but will be published on the conference website.
   
Both types of posters/demos will be displayed during the conference.

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Introduction
Participants are invited to submit posters and research demos to GreenCom 2015. GreenCom 2015 is created to provide a prime international forum for both researchers, industry practitioners and environment experts to exchange the latest fundamental advances in the state of the art and practice of Internet of Things as well as joint-venture and synergic research and development across various related areas. Topics of interest for posters and demos include, but not limited to:

Scope and Topics
 
A. Green Computing and Communication Technologies
• Green infrastructure sustainable design and technologies
• Energy- and power-constrained devices and gateways
• Ultra-low power systems architectures
• Low-power, distributed data processing on sensors
• Energy-efficient M2M wired and wireless communications and networking
• Optimization and/or analysis in green computing and communications (including core
network optimization)
• Green big data architecture
• Green cloud computing
• Energy efficient networking, communication and protocols
• Energy efficiency in networking, wireless networks and vehicular networks
• Energy efficiency in data centers and large-scale data processing
• Measurement and modeling of energy consumption
• Standardization and benchmark
   
B. Smart Energy and Smart Grid.
• Smart metering infrastructure and technologies
• Large-scale monitoring, control and demand response
• Advanced data fusion, mining and modeling in smart grid
• Management and control of distributed energy generation, storage and consumption
• Advanced smart grid applications: grid-to-vehicle and vehicle-to-grid, Micro-grid
• Renewable energy generation and new energy sources
• Standardization and benchmark
   
C. Green Society Applications
• Smart sensing systems
• Smart city
• Green vehicle, green home, green buildings and green anything
• Green industrial automation and control
• Intelligent Transport Systems and control
 

Chairs
William Liu, AUT, New Zealand
Surya Nepal, CSIRO, Australia




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Sunday 27 September 2015

TPNC 2015: call for posters





*To be removed from our mailing list, please respond to this message with UNSUBSCRIBE in the subject line*

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The 4th International Conference on the Theory and Practice of Natural Computing (TPNC 2015) invites authors to submit poster presentations. TPNC 2015 will be held in Mieres (Spain) on 15-16 December, 2015. See

http://grammars.grlmc.com/TPNC2015/

Poster presentations are intended to enhance informal interactions with the conference participants, at the same time allowing for in-depth discussion.

TOPICS

Authors are encouraged to submit presentations displaying novel work in progress on:

- nature-inspired models of computation,
- synthesizing nature by means of computation,
- nature-inspired materials,
- information processing in nature,
- applications of natural computing.

Posters do not need to show final research results. Work that might lead to new interesting developments is welcome.

KEY DATES

Submission deadline: November 8, 2015
Notification of poster acceptance or rejection: November 15, 2015

SUBMISSION

Please submit a .pdf abstract through:

https://www.easychair.org/conferences/?conf=tpnc2015

It should contain the title, author(s) and affiliation, and should not exceed 500 words.

PRESENTATION

Posters will be allocated 10 minutes each in the programme for oral presentation. Moreover, they will remain hanging out during the whole conference for discussion.

PUBLICATION

Posters will not appear in the LNCS proceedings volume of TPNC 2015. However, they will be eligible for submission to the post-conference journal special issue in Soft Computing (Springer).

REGISTRATION

At least one author of each accepted poster must register to the conference. Their registration fare is reduced: 225 Euro (appr. half of the cheapest fare for regular participants). Contributors of regular papers who in addition get a poster accepted must register for the latter too.


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Last CFP: ISPASS (IEEE Int. Symposium on Performance Analysis of Systems and Software)





After 16 years in the US, the ISPASS conference is now moving “abroad" for the first time. Welcome to Uppsala, Sweden, April 17-19 2016.
The name says it all:  IEEE International Symposium on Performance Analysis of Systems and Software.  The focus is on performance-related problems, solutions, methods and tools for software and system performance and power analysis and optimisation. As such, ISPASS is relevant for a large body of research in scientific computing and HPC. More info: www.ispass.org  
   
It would be really fun to have a large presence from this community at next ISPASS. Please spread the word...

Important dates:
• Paper Abstract submissions due: October 2
• Full submissions due:  October 9
• Rebuttal: January 12-13
• Notification of acceptance: January 22
• Final paper due: March 3

General Chair:
      Erik Hagersten, Uppsala University

Program Chair:
      Andreas Moshovos, University of Toronto

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Friday 25 September 2015

CfP: 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2016)





CALL FOR PAPERS - PDP 2016
24th Euromicro International Conference on
Parallel, Distributed, and Network-Based Processing

*** Extended Submission Deadline- 27 September 2015 ***

Aquila Atlantis Hotel, Heraklion, Crete, Greece, 17-19 Feb. 2016

Parallel, Distributed, and Network-Based Processing has undergone impressive changes over recent years. New architectures and applications have rapidly become the central focus of the discipline. These changes are often a result of cross-fertilization of parallel and distributed technologies with other rapidly evolving technologies. It is of paramount importance to review and assess these new developments in comparison with recent research achievements in well-established areas of parallel and distributed computing from industry and the scientific community. PDP 2016 will provide a forum for the presentation of these and other issues through original research presentations and will facilitate the exchange of knowledge and new ideas at the highest technical level.

Topics of interest include, but are not restricted to:
* Parallel Computing: massively parallel machines; embedded parallel and distributed systems; multi- and many-core systems; GPU and FPGA based parallel systems; parallel I/O; memory organization.
* Distributed and Network-based Computing: Cluster, Grid, Web and Cloud computing; mobile computing; interconnection networks.
* Big Data: large scale data processing; distributed databases and archives; large scale data management; metadata; data intensive applications.
* Models and Tools: programming languages and environments; runtime support systems; performance prediction and analysis; simulation of parallel and distributed systems.
* Systems and Architectures: novel system architectures; high data throughput architectures; service-oriented architectures; heterogeneous systems; shared-memory and message-passing systems; middleware and distributed operating systems; dependability and survivability; resource management. 
* Advanced Algorithms and Applications: distributed algorithms; multi-disciplinary applications; computations over irregular domains; numerical applications with multi-level parallelism; real-time distributed applications.

In addition, special sessions will address upcoming novel topics:
* GPU computing and Many Integrated Core Computing
* Formal Approaches to Parallel and Distributed Systems
* Advances in High-Performance Bioinformatics, Systems and  Synthetic Biology
* Security in Parallel, Distributed and Network-Based Computing
* Energy Efficient Management of Parallel Systems, Platforms, and  Computations
* Cloud Computing on Infrastructure as a Service and its  Applications
* High Performance Computing in Modelling and Simulation
* On-Chip Parallel and Network-Based Systems
* Multi-Core and Many-Core systems for Embedded Computing

IMPORTANT DATES
Paper submission: 20 September 2015  --> Extended to 27 September
Acceptance notification:  19 October 2015
Camera ready due:  10 November 2015
Conference:  17-19 February. 2016

SUBMISSION OF PAPERS:
Publication: All accepted papers, regular and short, will be included in the same volume, published by the Conference Publishing Services (CPS). The Final Paper Preparation and Submission Instructions will be published after the notification of acceptance. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be submitted to IEEE explore, CDSL, and for indexing among others, to DBLP, Scopus ScienceDirect, and ISI Web of Knowledge. Selected papers will be published in special issues of one or more journals.

Prospective authors should submit a full paper not exceeding 8 pages in the Conference proceedings format ( double-column, 10pt) to the conference main track or to Special Sessions through the EasyChair conference submission system (http://www.easychair.org/conferences/?conf=pdp2016) with an indication of the main track or the name of the Special Session. 

Double-bind review: the paper should not contain authors’ names and affiliations; in the reference list, references to the authors’ own work entries should be substituted with the string "omitted for blind review”.

ORGANIZERS:
General Co-chairs:
Yiannis Cotronis, cotronis@di.uoa.gr, University of Athens
Masoud Daneshtalab, masdan@kth.se, KTH, Sweden
George Papadopoulos, george@cs.ucy.ac.cy, University of Cyprus

Publication Chair:
Amund Skavhaug, Norwegian University of Science and Technology

Publicity Co-chairs:
Masoumeh Ebrahimi, University of Turku, Finland and KTH Sweden
Maurizio Palesi, KORE University, Italy

Contact: 
Yiannis Cotronis, cotronis@di.uoa.gr, University of Athens

ABOUT EUROMICRO
Euromicro is an international scientific organization advancing sciences and applications of Information Technology and Microelectronics. A major focus is on organizing conferences and workshops in Computer Science and Computer Engineering. Euromicro is a non-profit association founded in 1974 and annual conferences have taken place in more than 20 countries all over Europe. 

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Call for Participation: IISWC 2015





[Apologies if you receive multiple copies of this announcement]

HOTEL RESERVATION LINK:

******* CALL FOR PARTICIPATION : IISWC 2015 *******
2015 IEEE International Symposium on Workload Characterization
Atlanta, GA, October 4-6, 2015

We are pleased to invite you to attend the IEEE International Symposium on
Workload Characterization on October 4th – 6th, 2015, at the Georgia Tech Hotel
and Conference Center in Atlanta, Georgia.

IISWC is the only symposium of its kind anywhere.  If you are interested at all
with what computing workloads really look like today, IISWC is where you can
get answers.

Come join us in lovely midtown Atlanta on the Georgia Tech campus for 3-days of
learning, networking, and collaboration:


Best regards,
Sudhakar Yalamanchili and Hyesoon Kim, IISWC Program co-Chairs
Rich Vuduc and Tom Conte, IISWC General co-Chairs


TUTORIALS
SUNDAY, OCTOBER 4TH, 2015

Tutorial I: Contech: Modeling and Analyzing Parallel Programs with Task
Graphs (9am to 12:30pm)

Tutorial II: Wind River® Simics and Intel® SAE: Dynamic Binary Instrumentation
of OS Kernel, Driver and BIOS (9am to 12:30pm)

Tutorial III: Open-Source Benchmarks for Online Data-Intensive Services (1:30pm
to 5pm)

Tutorial IV: Sigil and SynchroTrace: Communication-Aware Workload Profiling and
Memory-NoC Simulation (1:30pm to 5pm)


PROGRAM

MONDAY, OCTOBER 5TH, 2015
________________________________________________________________________________

07:30 – 08:15 REGISTRATION
08.15 – 08:30 OPENING AND WELCOME
08:30 – 09:30 KEYNOTE ADDRESS
Workload Characterization in the Era of Specialization
David Brooks, Harvard University

09:30 – 10:00 BREAK 

10.00 – 12.00 PAPER SESSION 1: MOBILE APPLICATIONS

Big or Little: A Study of Mobile Interactive Applications on an Asymmetric
Multi-core Platform
Wonik Seo (KAIST), Daegil Im (Samsung Electronics), Jeongim Choi (KAIST),
Jaehyuk Huh (KAIST) 

I/O Characteristics of Smartphone Applications and Their Implications for eMMC
Design 
Deng Zhou (San Diego State University), Wen Pan (San Diego State University),
Wei Wang (San Diego State University, Tao Xie (San Diego State University)

Characterization and Throttling-based Mitigation of Memory Interference for
Heterogeneous Smartphones 
Davesh Shingari (Arizona State University), Akhil Arunkumar (Arizona State
University), Carole-Jean Wu (Arizona State University)

Energy-Performance Trade-offs on Energy-Constrained Devices with
Multi-Component DVFS 
Rizwana Begum (Drexel Univeristy), Guru Prasad Srinivasa (University at
Buffalo), David Werner (Drexel Univeristy), Mark Hempstead (Drexel
Univeristy), Geoffrey Challen (Drexel University) 

12:00 – 13:00 LUNCH

13:00 – 14:30 PAPER SESSION 2: BEST PAPER NOMINEES 

CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on
Futuristic Multicores 
Masab Ahmad (University of Connecticut), Farrukh Hijaz (University of
Connecticut), Qingchuan Shi (University of Connecticut), Omer Khan
(University of Connecticut)
   
Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge
Server 
Scott Beamer (UC Berkeley), Krste Asanovic (UC Berkeley), David Patterson (UC
Berkeley)  

Performance Characterization for High-Level Programming Models for GPU Graph
Analytics 
Yuduo Wu (University of California,  Davis),  Yangzihao Wang (University of
California, Davis), Yuechao Pan (University of California, Davis), Carl
Yang (University of California, Davis), John D. Owens (University of
California, Davis)
   
14:30 – 15:00 BREAK

15:00 – 16:30 PAPER SESSION 3: GPUS I

Fast Computational GPU Design with GT-Pin 
Melanie Kambadur(Columbia University), Sunpyo Hong (Intel), Juan Cabra
(Intel), Harish Patil (Intel), Chi-Keung Luk (Intel), Sohaib Sajid (Intel),
Martha A. Kim (Columbia University)

GPU Computing Pipeline Inefficiencies and Optimization Opportunities in
Heterogeneous CPU-GPU Processors 
Joel Hestness (University of Wisconsin – Madison), Stephen W. Keckler (NVIDIA
and University of Texas – Austin), David A. Wood (University of Wisconsin –
Madison) 

Exploring Parallel Programming Models for Heterogeneous Computing Systems 
Mayank Daga (AMD), Zachary S. Tschirhart (AMD), Chip Freitag (AMD) 

16:30 – 18:00 POSTER SESSION

On Power-Performance Characterization of Concurrent Throughput Kernels
Nilanjan Goswami (University of Florida), Yuhai Li (University of Florida),
Amer Qouneh (University of Florida), Chao Li (Shanghai Jiao Tong University),
Tao Li (University of Florida) 

Retrospective Look Back on the Road Towards Energy Proportionality 
Daniel Wong (University of Southern California), Julia Chen (University of
Southern California), Murali Annavaram (University of Southern California)

Characterization of Shared Library Access Patterns of Android Applications
Xiaowan Dong (University of Rochester), Sandhya Dwarkadas (University of
Rochester), Alan Cox (Rice University) 

Characterizing Data Analytics Workloads on Intel Xeon Phi 
Biwei Xie (ICT CAS), Xu Liu (College of William and Mary), JianFeng Zhan(ICT
CAS), Zhen Jia (ICT CAS), Yuqing Zhu(ICT CAS), Lei Wang (ICT CAS), Lixin
Zhang (ICT CAS)

How Good Are Low-Power 64-bit SoCs for Server-Class Workloads?
Reza Azimi (Brown University), Xin Zhan (Brown University), Sherief Reda
(Brown University)

A Taxonomy of GPGPU Performance Scaling
Abhinandan Majumdar (Cornell University), Gene Wu (The University of Texas at
Austin), Kapil Dev (Brown University), Joseph L. Greathouse (Advanced Micro
Devices), Indrani Paul (Advanced Micro Devices), Wei Huang (Advanced Micro
Devices), Arjun-Karthik Venugopal (Advanced Micro Devices), Leonardo Piga
(Advanced Micro Devices), Chip Freitag (Advanced Micro Devices), Sooraj Puthoor
(Advanced Micro Devices)

TUESDAY, OCTOBER 6TH, 2015
________________________________________________________________________________

08:30 – 9:30 KEYNOTE ADDRESS
Commercial Big Data Workloads, Lessons from the Industry.
Flavio Villanustre, VP Technology, LexisNexis Risk Solutions

09:40 – 10:40  PAPER SESSION 4:  GPUS II 

Revealing Critical Loads and Hidden Data Locality in GPGPU applications 
Gunjae Koo (University of Southern California), Hyeran Jeon (University of
Southern California), Murali Annavaram (University of Southern California)

3D Workload Subsetting for GPU architecture Pathfinding 
Vinod Mohan George (Intel)

10:40 – 11:00 BREAK 

11:00 – 12:30  PAPER SESSION 5: SYSTEMS

PC Design Use and Purchase Relations
Al M. Rashid (Intel Corporation), Bob Kuhn (Intel Corporation), Bijan Arbab
(Intel Corporation), David Kuck (Intel Corporation)

Characterizing Disk Failures with Quantified Disk Degradation Signatures: An
Early Experience 
Song Huang (University of North Texas), Song Fu (University of North Texas),
Quan Zhang (Wayne State University), Weisong Shi (Wayne State University)

SourceMark: A Source-Level Approach for Identifying Architecture and
Optimization Agnostic Regions for Performance Analysis
Abhinav Agrawal (North Carolina State University), Bagus Wibowo (North Carolina
State University), James Tuck (North Carolina State University)

12.30 – 13:30 LUNCH

13.30 – 14.30  PAPER SESSION 6: SIMULATION 

Differential Fault Injection on Microarchitectural Simulators 
Manolis Kaliorakis (University of Athens), Sotiris Tselonis (University of
Athens), Athanasios Chatzidimitriou (University of Athens), Nikos Foutris
(University of Athens), Dimitris Gizopoulos (University of Athens)

Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed 
Andreas Sandberg (Uppsala University), Nikos Nikoleris (Uppsala University),
Trevor E. Carlson (Uppsala University), Erik Hagersten (Uppsala University),
Stefanos Kaxiras (Uppsala University), David Black-Schaffer (Uppsala
University)

14:30 – 15:00 BREAK


15:00 – 16.30  PAPER SESSION 7 
DATA CENTER AND CLOUD 

Power Aware NUMA Scheduler in VMware's ESXi Hypervisor 
Qasim Ali (VMware), Haoqiang Zheng (VMware), Tim Mann (VMWare), Raghunathan
Srinivasan (Intel)

Evaluating the Combined Impact of Node Architecture and Cloud Workload
Characteristics on Performance
Diman Zad Tootaghaj (The Pennsylvania State University), Farshid Farhat (The
Pennsylvania State University), Mohammad Arjomand (The Pennsylvania State
University), Paolo Faraboschi (HP Labs), Mahmut Taylan Kandemir (The
Pennsylvania State University), Anand Sivasubramaniam (The Pennsylvania State
University), Chita R. Das (The Pennsylvania State University)

Quantifying the Performance Impact of Memory Latency and Bandwidth for Big Data
Workloads 
Russell Clapp (Intel Corporation), Martin Dimitrov (Intel Corporation), Karthik
Kumar (Intel Corporation), Vish Viswanathan (Intel Corporation), Thomas
Willhalm (Intel Gmbh)

16:30 – BEST PAPER AWARD AND CLOSING


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Wednesday 23 September 2015

Call for Papers: ICAC 2016: 13th IEEE International Conference on Autonomic Computing





Please excuse if you receive multiple copies of this CfP.
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ICAC 2016 Call for Papers
http://icac2016.uni-wuerzburg.de/

13th IEEE International Conference on Autonomic Computing (ICAC 2016)
Wuerzburg, Germany, July 19-22, 2016

In cooperation with USENIX and SPEC
___________________________________________________________________
IMPORTANT DATES

Abstract Submission:               January 14, 2016
Paper Submission:                  January 21, 2016
Author Notification:               April 15, 2016
Final Manuscript:                  May 1, 2016
Conference                         July 19-22, 2016

Doctoral Symposium Submissions:    January 31, 2016
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SCOPE AND TOPICS

ICAC is the leading conference on autonomic computing, its foundations, principles, engineering, technologies, and applications. Nowadays, complex systems of all types, like large-scale data centers, cloud computing infrastructures, cyber-physical systems, the internet of things, and similar, are increasingly complex, involving many active, interconnected components requiring careful coordination. Being impossible for a human to manage such systems, the autonomic computing paradigm with its support for self-management capabilities becomes increasingly indispensable for the components of our IT world.

The conference seeks latest research advances on science and engineering concerning all aspects of autonomic computing, including but not limited to the following main research topics:

* Foundations
  - Fundamental science and theory of autonomic computing systems and feedback
    control for software, self-awareness and self-expression
  - Algorithms, such as AI, machine learning, control theory, operations
    research, probability and stochastic processes, queueing theory, rule-based
    systems, biological-inspired techniques, and socially-inspired techniques
  - Formal models and analysis of self-management, emergent behavior,
    uncertainty, self-organization, self-awareness, trustworthiness

* Resource Management in Data Centers
  - Hypervisors, operating systems, middleware, and platforms for self-managing
    data centers and cloud infrastructures
  - Sensing, energy efficiency, and resource adaptation
  - Autonomic components, such as multi-core servers, storage, networking, and
    hardware accelerators
  - Applications and case studies of end-to-end design and implementation of
    systems for resource management

* Cyber-Physical Systems (CPS) and Internet of Things (IoT)
  - System architectures OS, services, middleware, and protocols for CPS and IoT
  - Energy, real-time, and mobility management
  - Design principles, methodologies, and tools for CPS and IoT
  - Self-organization under severe resource constraints
  - Applications and case studies of autonomic CPS and IoT

* Self-Organization and Organic Computing
  - Self-organization principles and organic computing principles borrowed from
    systems theory, control theory, game theory, decision theory, social   
    theories, biological theories, etc.
  - Self-organization, emergent behavior, decentralized control, individual and
    social/organizational learning, scalability, robustness, goal- and norm-
    governed behavior, online self-integration for trustworthy self-organizing
    and organic systems
  - Infrastructures and architectures for self-organizing systems and organic
    computing systems
  - Applications and case studies for self-organization and organic computing

* Emerging Computing Paradigms: Cognitive Computing, Self-Aware Computing       
  - Advanced learning for cognitive computing such as meta-cognitive learning,
    self-regulatory learning, consciousness and cognition in learning,
    collaborative / competitive learning, and online / sequential learning
  - Architectures, control, algorithmic approaches, instrumentation, and
    infrastructure for cognitive computing and self-aware systems
  - Cognitive computing and self-awareness in heterogeneous and decentralized
    systems
  - Applications and case studies for social networks, big data systems, deep
    learning systems, games, and artificial assistants, cognitive robots, and
    systems with self-awareness and self-expression 

* Software Engineering for Autonomic Computing Systems: Architecture,
  Specifications, Assurances
  - Design methodology, frameworks, principles, infrastructures, and tools for
    development and assurances for autonomic computing systems
  - System architectures, services, components and platforms broadly applicable
    for autonomic computing system engineering
  - Goal specification and policies, modeling of service-level agreements,
    behavior enforcement, IT governance, and business-driven IT management
  - Applications and case studies for software engineering approaches for
    autonomic computing systems

In addition to fundamental results ICAC is also interested in applications and experiences with prototyped or deployed systems solving real-world problems in science, engineering, business, or society. Typical application areas for ICAC are autonomous robotics, cloud computing, cyber-physical systems, data centers, dependable computing, industrial internet / industry 4.0, internet of things, mobile computing, service-oriented systems, smart buildings, smart city, smart grid / energy management, smart factory, smart user interfaces, space applications, and traffic management.

This year a doctoral symposium will be organized as part of ICAC. For more information see
http://icac2016.uni-wuerzburg.de/calls/doctoral-symposium/

All papers must represent original and unpublished work that is not currently under review. Submissions are required to mark at least one topic area. Papers will be reviewed by at least three PC members including at least two having specific domain expertise concerning the indicated main research topics and judged on originality, significance, interest, correctness, clarity, and relevance to the broader community. At least one author of each accepted paper is expected to attend the conference.

Papers can be submitted in one of the following three categories with different acceptance criteria for each category:

* Full research papers limited to 10 pages (double column, IEEE format)
* Experience papers limited to 8 pages (double column, IEEE format)
* Short papers limited to 6 pages (double column, IEEE format)

Full and experience research papers are strongly encouraged to report on experiences, measurements, user studies, and provide an appropriate quantitative evaluation if at all possible. Short papers can either be work in progress, or position and challenge papers that motivate the community to address new challenges. See the conference website for format instructions. Papers must be submitted electronically in PDF format through the ICAC’2016 submission site.

There will be a BEST PAPER AWARD for the full research paper category and it is panned that a selection of the best papers of the full research paper category will be invited to submit an extended version of their contribution for a ICAC 2016 SPECIAL ISSUE after the conference.

___________________________________________________________________

ORGANIZATION

General Chair
    Samuel Kounev, University of Wuerzburg, Germany

Program Committee Co-Chairs
    Holger Giese, Hasso Plattner Institute, Germany
    Jie Liu, Microsoft Research, Redmond, USA

Workshop Chair
    Lydia Chen, IBM Zurich, Switzerland

Publicity Co-Chairs
    Giacomo Cabri, Universita di Modena e Reggio Emilia, Italy
    Javier Camara, Carnegie Mellon University, Pittsburgh, USA
    Nikolas Herbst, University of Wuerzburg, Germany
    Jianguo Yao, Shanghai Jiao Tong University, China

Finance Chair
    Philippe Lalanda, University of Grenoble, France

Proceedings Chair
    Daniel Gmach, HP Labs, USA

Poster and Demo Chair
    Stephanie Chollet, Grenoble INP Esisar/LCIS, France

Local Arrangements and Web Chair
    Lukas Ifflaender, University of Wuerzburg, Germany

Doctoral Symposium Chair
    Christian Becker, University of Mannheim, Germany
    Evgenia Smirni, College of William and Mary, USA
___________________________________________________________________

PROGRAM COMMITTEE

    http://icac2016.uni-wuerzburg.de/committees/program-committee/





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CFP - MICPRO - Special Issue on Sustainable Processor Architectures and Applications





[Apologies if you receive multiple copies of this CFP]

CALL FOR PAPERS

Special Issue on 
Sustainable Processor Architectures and Applications
Journal of Microprocessors and Microsystems

Guest Editors
* Fangyang Shen, New York City College of Technology
* Mei Yang, University of Nevada, Las Vegas
* Maurizio Palesi, Kore University, Italy

Theme
This special issue attempts to create a platform to foster new ideas
and technical insights in the fields of energy-efficient and
sustainable processor architectures and systems and their scientific,
engineering, biomedical, and commercial applications. In particular,
we would like to focus on issues on sustainable multi/many-core
computing and programming, cloud computing, system-on-chip
architectures/systems, application-specific multiprocessor
architectures/systems, and application support. We invite submissions
of regular papers with unpublished original results and, by
invitation, the revised and extended version of the papers presented
in the High-Performance Computing Architectures (HPCA) Track at the
12th International Conference on Information Technology: New
Generation (ITNG) and Euromicro DSD'2015 Conference.

Specific Topics
Topics of interest include, but are not limited to, the following:
* Power- and thermal-aware multi/many-core processor architectures
* Low-power system-on-chip (SoC) and network-on-chip (NoC)
  architectures
* Energy-efficient application-specific multiprocessor
  architectures/systems
* Power- and thermal-aware algorithms and software for on-chip
  applications
* Power and temperature modeling and monitoring mechanisms for on-chip
  systems
* Energy-efficient application modeling and mapping schemes for
  on-chip systems
* Energy-efficient parallelization and scheduling methodologies for
  multi/many-core systems
* Parallel programming models and compiler design for multi/many-core
  systems
* High performance computing and its scientific, engineering,
  biomedical, and commercial applications
* MapReduce and cloud computing for data-intensive processing
* System/application support for power and thermal management
* System/application support for multithreading, synchronization, and
  parallelism
* Debugger and performance analysis tools for multi/many-core
  processors

Journal Guide for Authors
All submitted papers will be peer-reviewed. Accepted manuscripts must
conform to the journal guide for Authors on:

Important Deadlines
* Submission of special issue manuscript: Oct. 15, 2015
* Notification of special issue acceptance: Dec. 15, 2015
* Submission of final journal version: Feb. 1, 2016


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Tuesday 22 September 2015

ASPLOS 2016: Call for Tutorials





Call For Tutorial Proposals - ASPLOS 2016

————————

Tutorial proposals are solicited for ASPLOS-2016, Atlanta, GA.
Tutorials will be held on April 2, 2016 (Saturday) and April 3, 2016 (Sunday).

http://www.ece.cmu.edu/calcm/asplos2016/

Proposals for both half- and full-day tutorials are solicited on any topic that
is relevant to the ASPLOS audience. Tutorials that focus on tools and techniques
that enable research across layers of the computational stack are strongly
encouraged.

In previous years, tutorials seeking to achieve any of the following goals have
been particularly successful:

- Describe an important piece of research infrastructure.
- Educate the community on an emerging topic.

Submission Procedures

Proposals should provide the following information:

• Title
• Presenter(s) and contact information.
• Proposed duration (full day, half day).
• 1-2 paragraph abstract suitable for tutorial publicity.
• 1 paragraph biography per presenter suitable for tutorial publicity.
• 1-3 page description (for evaluation). This should include:

- Tutorial scope and objectives
- Topics to be covered
- Target audience
- Expected number of attendees
- If the tutorial has been held previously, the location (i.e., conference),
date, and number of attendees.

Proposals should be submitted via e-mail to Tushar Krishna
(tushar@ece.gatech.edu) with the subject "ASPLOS2016 Tutorial Proposal".
Submissions will be acknowledged via e-mail.

Important Dates

----------------

Submission deadline: Tuesday, November 17, 2015
Notification: Tuesday, November 24, 2015

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RST track @ SAC - Submission extended to 28 Sep.





      ****   Final deadline extension:  28 September   ****

-------------------------------------------------------------------
     31st ACM/SIGAPP SAC Symposium on Applied Computing
               April 4-8, 2016. Pisa, Italy.

                    T r a c k    R S T 
                    
   RELIABLE SOFTWARE TECHNOLOGIES AND COMMUNICATION MIDDLEWARE
   
                     http://rstsac.uc3m.es
                     
                 C a l l    f o r   P a p e r s
 --------------------------------------------------------------------

   
IMPORTANT DATES

Full paper submission:    September 28,  (Final deadline)
Author notification:      November 13, 2015
Camera ready paper:       December 11, 2015
-------- 
JOURNAL SPECIAL ISSUE in FUTURE GENERATION COMPUTER SYSTEMS
(Elsevier). FGCS is a JCR indexed journal with a 2.786 impact 
factor in 2014 (5-Year Impact Factor 2.464).
SI will be compiled from the best submissions to RST track.
--------

     
Topics include (but are not limited to): 

-Reliable and time-sensitive distribution models 
-Performance of distributed applications 
-Cloud computing advances for cyber-physical systems and mobile cloud computing. 
-Middleware for the efficient integration of cyber-physical systems and the cloud 
-Reactive stream processing and on line processing of big data flows 
-Efficient integration with the run-time support: operating systems and virtualization technology 
-QoS-aware middleware for datacenter resource management 
-Interaction models (e.g., publish-subscribe or event-based). 
-Programming models and languages 
-Efficient and context-aware server-side management of smart city data 
-Scalability in city-wide deployment scenarios



PAPER SUBMISSION

Manuscripts must be submitted electronically in PDF format (6 pages in
ACM conf style), according to the instructions contained in the track
web site  http://rstsac.uc3m.es. Contributions must contain original
unpublished work not concurrently submitted to other conferences or journals. 



TRACK CHAIRS

Marisol Garcia-Valls - Universidad Carlos III de Madrid, Spain
Aniruddha Gokhale    - Vanderbilt University, USA
Paolo Bellavista     - University of Bologna, Italy



PROGRAM COMMITTEE

Kyongho An, RTI, USA 
Roberto Baldoni, Universita di Roma La Sapienza, Italy
Ken Birman, Cornell University, USA
Gordon Blair, University Lancaster, UK
Cristian Borcea, New Jersey Institute Tech, USA
Jian-nong Cao, Honk Kong PolyU, Hong Kong 
Mauro Caporuscio, Linnaeus University, Sweden 
Antonio Cassimiro, University of Lisbon, Portugal
Abhishek Dubey, Vanderbilt University, USA 
Paul Ezhilchelvan, Newcastle University, UK 
Nikolaos Georgantas, Inria, France
Akram Hakiri, LAAS CNRS, France 
Joe Hoffert, Indiana Wesleyan University, USA
Ruediger Kapitza, Technische Universitaet Braunschweig, Germany 
Takayuki Kuroda, NEC, Japan 
Cong Liu, University of Texas Dallas, USA 
Juan Lopez-Soler, University of Granada, Spain 
Pedro J. Marron, University Duisburg-Essen, Germany 
William Otte, Vanderbilt University, USA
Karthik Pattabiraman, University of British Columbia, Canada
Leonardo Querzoni, Universita di Roma La Sapienza, Italy
Valerio Schiavoni, Univerity Neuchatel, Switzerland 
Anders Ravn, Aalborg University, Denmark
Binoy Ravindran, Virginia Tech, USA
Stefano Russo, University of Naples, Italy 
Michael Wahler, ABB, Switzerland
Tomofumi Yuki, Inria, France


--
MARISOL GARCIA VALLS
Universidad Carlos III de Madrid

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CfP: AISTECS workshop @ HiPEAC 2016





[Please accept our apologies if you receive multiple copies of this message.]

----------------------------------------------------------------------------------------------------------------
Call for Papers

AISTECS 2016
1st International Workshop on
Advanced Interconnect Solutions and Technologies for Emerging Computing Systems
http://mpsoc.unife.it/~aistecs/

Associated with the
11th HiPEAC Conference on High Performance and Embedded Architecture and Compilers
January 18–20, 2016, Prague, Czech Republic
https://www.hipeac.net/2016/prague/
----------------------------------------------------------------------------------------------------------------

This workshop is a new format blending the successful INA-OCMC workshop (nine editions
at HiPEAC) and the envelope-pushing Silicon Photonics workshop (two editions at HiPEAC)
into one combined instance.

Scalable interconnect architectures form the solid base on top of which future complex
computing platforms will be developed. The interconnect architecture should be as high
performance as its connecting nodes, thus enabling the expected exponential growth in
system concurrency. The number of nodes either on-chip or off-chip that need to
communicate in modern embedded and HPC systems is constantly increasing. This trend
poses significant challenges to the interconnection network designers that tackle a
multidimensional problem involving hardware and software components such as network
interfaces, switches, and communication library APIs.

At the same time, new usage models of mobile devices together with the digital
convergence trend require that largely different operating conditions are accommodated
by a single, deeply reconfigurable design. In this direction, heterogeneity could take the
form of runtime specialization rather than design time customization. Similarly,
manufacturing yield and device availability could be significantly improved by the device
capability to adapt to hardly predictable and even changing operating conditions at runtime.

With Exascale systems on the horizon, we will be ushering in an era with power and energy
consumption as the primary concerns for scalable computing. To achieve viable high
performance, revolutionary methods are required with a stronger integration among
hardware features, system software and applications.

A main purpose of this workshop is to promote further research interests and activities on
Silicon Photonics and related topics in the perspective of its adoption in future high
performance systems and, in general, within future computing systems (from
servers/workstations down to embedded devices). In fact, Silicon Photonics poses in itself
crucial challenges and interesting design tradeoffs for being deployed in future computer
systems effectively, also in integration with other technologies. Furthermore, the unique
features of photonics (e.g. extreme low-latency, end-to-end transmission, high bandwidth
density) have the potential to constitute a discontinuity element able to modify the expected
shape of future computer systems from the design point of view and also from the
programmability and/or runtime management perspectives.

The AISTECS workshop aims to increase the synergy from a complete range of viewpoints,
from raw technology issues and solutions up to studies at the overall system level of modern
multi-/many-core systems, both from academic and industrial researchers working in this
area. We are interested in experimental, systems-related, and work-in-progress papers in all
aspects of interconnects in general and SiP technology in particular at all levels of
development.

We invite contributions of previously unpublished results on all aspects of interconnection
network architectures and SiP that include but are not limited to:
 - Networks on Chip (NoC)
 - Multi-chip interconnection networks, including Cluster Interconnects
 - Communication architectures for 2,5D and 3D stacked systems
 - Switching, buffering, and routing architectures
 - Reconfigurable/programmable interconnect components
 - Photonics in the on-chip and inter-chip interconnections, memory hierarchy and I/O of
   computing systems, in future homogeneous/heterogeneous CMPs
 - On-chip and off-chip optical interconnection for HPC systems and datacenters
 - Crucial challenges and design tradeoffs for Silicon Photonics (SiP) in future computer
   systems
 - Integration of SiP with other technologies
 - Silicon photonics low-level technological improvements and implications for computer
   system communication
 - Thermal-/energy- and power-related issues and solutions
 - Asynchronous interconnect designs
 - Interaction with memory hierarchy
 - Architectures for QoS support and coherency
 - Topology exploration
 - Impact of the interconnect on application performance
 - Reliability, availability, fault tolerance
 - Programming models for communication-centric systems
 - Synergies and tradeoffs between photonic and electronic network technologies

SUBMISSION AND DATES

Submitted papers must represent original, previously unpublished, research that is not
currently under review for any other workshop, conference or journal. All manuscripts will be
reviewed by an international Program Committee and will be judged on correctness, originality,
technical strength, significance, quality of presentation, interest, and relevance to the workshop
attendees. The submission and review process will be handled electronically via EasyChair:
https://easychair.org/conferences/?conf=1staistecs.

Papers must be in PDF format and should include title, authors and affiliations as well as the
e-mail address of the contact author. Papers must be formatted in accordance to the
double-column CPS format (http://www.computer.org/web/cs-cps/authors). Word and LaTeX
style templates will be available on the website. The workshop encourages four-pages
work-in-progress submissions, with a maximum of six pages for more developed work.
Submissions must be limited to six A4 pages, including figures and references. Papers
deviating significantly from the paper size and formatting rules may be rejected without review.

* Submission deadline: November 2, 2015
* Author notification: November 25, 2015
* Camera-ready paper due: December 4, 2015

PUBLICATION

The proceedings of the workshop will be published by Conference Publishing Services (CPS).
Conference proceedings will be submitted for indexing and inclusion in Xplore and CSDL.
Content will be submitted to the indexing companies for possible indexing. Indexing services are
independent organizations, and we cannot guarantee that any particular abstract or index entry
will be included in Ei Compendex or any other indexing service.

REGISTRATION

Authors of accepted papers are expected to register for and present their papers at the workshop.
Registration will be handled via the HiPEAC Conference.

WORKSHOP ORGANIZERS

General Chair:
* Sören Sonntag (Intel, Germany)
* Sandro Bartolini (Università di Siena, Italy)

Program Chairs:
* Giorgos Dimitrakopoulos (Democritus University of Thrace, Greece)
* José M. García (University of Murcia, Spain)

Publication Chair:
* Bogdan Prisacari (IBM Research Zurich, Switzerland)

Web Chair:
* Marco Balboni (University of Ferrara, Italy)

Steering Committee:
* José Duato (Technical University of Valencia, Spain)
* Manolis Katevenis (FORTH, Greece)
* Davide Bertozzi (University of Ferrara, Italy)
* Cyriel Minkenberg (IBM Research Zurich, Switzerland)

Program Committee (to be confirmed):
* Federico Angiolini, iNoCs, Switzerland
* José M. Cecilia, UCAM Murcia, Spain
* Marcello Coppola, STMicroelectronics, France
* Pierfrancesco Foglia, University of Pisa, Italy
* Holger Fröning, University of Heidelberg, Germany
* Francisco Gilabert, Intel, Germany
* Jose Angel Gregorio Monasterio, University of Cantabria, Spain
* Paolo Grani, University of California - St. Davis, USA
* Timothy Jones, University of Cambridge, UK
* Kostas Katrinis, IBM, Ireland
* Sébastien Le Beux, Lyon Institute of Nanotechnology (INL), France
* Hiroki Matsutani, Keio University, Japan
* Gokhan Memik, Northwestern University, USA
* Sergei Mingaleev, VPIphotonics, Germany
* Chrysostomos Nicopoulos, University of Cyprus, Cyprus
* Sudeep Pasricha, Colorado State University, USA
* Nikos Pleros, Aristotle University of Thessaloniki, Greece
* Sven Arne Reinemo, Simula, Norway
* Sebastien Rumley, Columbia University, USA
* Julio Sahuquillo, Universitat Politècnica de València, Spain
* José Luis Sánchez, University of Castilla-La Mancha, Spain
* Laurent Schares, IBM TJ Watson, USA
* Federico Silla, Universitat Politècnica de València, Spain
* Philip M. Watts, University College London, UK
* Eitan Zahavi, Mellanox, Israel
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Monday 21 September 2015

[IC2E'15] Call for Industry Papers - IEEE International Conference on Cloud Engineering (IC2E)





Call for Industry Papers - IEEE International Conference on Cloud Engineering (IC2E)

April 4-8, 2016 - Berlin, Germany

The Industrial Track of the IC2E 2016 solicits papers for presentation at the conference and inclusion in the conference proceedings. The purpose of the Industrial Track is to emphasize practical experience in applying recent research advances to real-world cloud engineering problems, and to disseminate information of particular interest to developers, practitioners, and others involved in practical, large-scale cloud systems.  Examples of these key areas include:

    Design choices and practical deployments in IaaS, PaaS, SaaS, etc.
    Experience with cloud management systems, tools, and integration
    Experience with cloud-based data management and analytics
    Scalability, availability, robustness, and failure recovery in the cloud
    Performance analysis, workload characterization and optimization in the cloud
    Life cycle management of cloud-based applications and services
    DevOps challenges: Interoperability, versioning, compatibility, and dependencies
    Economics: Metering, pricing, billing, monitoring
    Open source cloud technologies
    Customer experience and cloud usability studies

Papers must not exceed 8 pages (IEEE style), including abstract, all figures, tables, and references. Submitted papers should follow the general IC2E formatting instructions. Submitted papers may not be submitted for conference publication, journal publication, or be under review for any other conference or journal. For any questions regarding this, please contact the program chair.

Key Deadlines

    Paper Submission Deadline: October 30, 2015
    Notification of Acceptance: December 15, 2015
    Final Manuscripts Due: January 15, 2015

Web Submission Form
https://easychair.org/conferences/?conf=ic2e2016


Program Committee Chair
    Shu Tao, IBM Watson Research, USA

Program Committee Members
    Bharath Balasubramanian, AT&T Labs Research
    Lydia Chen, IBM Research Zurich Lab
    Yanpei Chen, Cloudera
    Devarshi Ghoshal, Lawrence Berkeley National Lab
    David Irwin, UMass-Amherst
    Hui Kang, IBM T J Watson Research Center
    Partha Kanuparthy, Yahoo Labs
    Youngjae Kim, Oak Ridge National Laboratory
    Rahul Potharaju, Microsoft
    Anees Shaikh, Google
    Chengwei Wang, AT&T Labs Research
    Guohui Wang, Facebook
    Rich Wolski, UCSB

--
Ningfang Mi
Assistant Professor
Department of Electrical and Computer Engineering 
Northeastern University
www.ece.neu.edu/~ningfang

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CFP: Performance Modeling, Benchmarking and Simulation (PMBS) Late Breaking Research Short Papers, Supercomputing 2015 (SC15), Austin, TX





===============================================================
     6th International Workshop on Performance Modeling,
               Benchmarking and Simulation of
              High Performance Computer Systems
                         (PMBS15)

  held as part of SC15, Austin, TX, November 2015

               http://www.pmbsworkshop.org
===============================================================


The PMBS15 workshop is concerned with the comparison of
high-performance computing systems through performance modeling,
benchmarking or through the use of tools such as simulators.

We are particularly interested in research which reports the
ability to measure and make tradeoffs in software/hardware
co-design to improve sustained application performance. We are
also keen to capture the assessment of future systems, for
example through work that ensures continued application
scalability through peta- and exa-scale systems.

The aim of this workshop is to bring together researchers, from
industry and academia, concerned with the qualitative and
quantitative evaluation and modeling of high-performance
computing systems. Authors are invited to submit novel research
in all areas of performance modeling, benchmarking and
simulation, and we welcome research that brings together current
theory and practice. We recognize that the coverage of the term
'performance' has broadened to include power consumption and
reliability, and that performance modeling is practiced through
analytical methods and approaches based on software tools and
simulators.

=== Topics of Interest ===

We encourage submissions in the following areas:

- Performance modeling, analysis, and prediction of applications
   and high-performance computing systems
- Novel techniques and tools for performance evaluation and
   prediction
- Advanced simulation techniques and tools
- Micro-benchmarking, application benchmarking and tracing
- Performance-driven code optimization and scalability analysis
- Verification and validation of performance models
- Benchmarking and performance analysis of novel hardware
- Performance concerns in software/hardware co-design
- Tuning and auto-tuning of HPC applications and algorithms
- Benchmark suites
- Performance visualisation
- Real-world case studies
- Studies of novel hardware such as Intel Xeon Phi co-processor
   technology, NVIDIA Kepler GPUs and AMD Fusion APU

Work which examines similar topics will also be considered.

=== Submission Guidelines ===

Authors are invited to submit full papers with unpublished, 
original work of not more than 10 pages of double column text 
using single spaced fonts on pages of 8.5 x 11 inches (this limit
includes all figures, content etc but does not include 
references). All papers should be formatted using the ACM style

A separate Late-Breaking Research and Preliminary Techniques 
stream is also available for authors to submit 5-page papers 
describing initial research or early first-of-a-kind results 
(this page limit does not include references but includes all 
technical content and figures). These papers will be presented 
in a dedicated, interactive session at PMBS15 enabling open 
discussion with industry and domain experts.

All accepted papers (subject to post-review revisions) will be 
published in the ACM digital and IEEE Xplore libraries by ACM 
SIGHPC.

Authors of selected papers will also be invited to submit revised
manuscripts for inclusion in special issues of two high 
performance computing journals (pending).

Papers should be submitted using EasyChair at: 

=== Important Dates ===

Full Paper Submissions - *PASSED*
Full Paper Notifications - September 28th 2015
Camera Ready Papers Due - October 5th 2015
Late Breaking Paper Submissions - October 13th 2015 (23:59 PST)
Late Breaking Paper Notifications - October 23rd 2015
PMBS15 Workshop - November 15th 2015
Supercomputing Conference Dates - November 15th - 20th 2015

=== More Information ===

For more information consult the PMBS Workshop homepage at:


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