CFP: Workshop on Virtualization in High­-Performance Cloud Computing (VHPC '16)

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====================================================================

CALL FOR PAPERS

11th Workshop on Virtualization in High­-Performance Cloud Computing (VHPC '16)

held in conjunction with the International Supercomputing Conference - High Performance,

June 19-23, 2016, Frankfurt, Germany.

====================================================================

Date: June 23, 2016

Workshop URL: http://vhpc.org

Lightning talk abstract registration deadline: February 29, 2016

Paper/publishing track abstract registration deadline: March 21, 2016

Paper Submission Deadline: April 25, 2016

Call for Papers

Virtualization technologies constitute a key enabling factor for flexible resource

management in modern data centers, and particularly in cloud environments.

Cloud providers need to manage complex infrastructures in a seamless fashion to support

the highly dynamic and heterogeneous workloads and hosted applications customers

deploy. Similarly, HPC environments have been increasingly adopting techniques that

enable flexible management of vast computing and networking resources, close to marginal

provisioning cost, which is unprecedented in the history of scientific and commercial

computing.

Various virtualization technologies contribute to the overall picture in different ways: machine

virtualization, with its capability to enable consolidation of multiple under­utilized servers with

heterogeneous software and operating systems (OSes), and its capability to live­-migrate a

fully operating virtual machine (VM) with a very short downtime, enables novel and dynamic

ways to manage physical servers; OS-­level virtualization (i.e., containerization), with its

capability to isolate multiple user­-space environments and to allow for their co­existence

within the same OS kernel, promises to provide many of the advantages of machine

virtualization with high levels of responsiveness and performance; I/O Virtualization allows

physical NICs/HBAs to take traffic from multiple VMs or containers; network virtualization,

with its capability to create logical network overlays that are independent of the underlying

physical topology and IP addressing, provides the fundamental ground on top of which

evolved network services can be realized with an unprecedented level of dynamicity and

flexibility; the increasingly adopted paradigm of Software-­Defined Networking (SDN)

promises to extend this flexibility to the control and data planes of network paths.

Topics of Interest

The VHPC program committee solicits original, high-quality submissions related to

virtualization across the entire software stack with a special focus on the intersection of HPC

and the cloud. Topics include, but are not limited to:

- Virtualization in supercomputing environments, HPC clusters, cloud HPC and grids

- OS-level virtualization including container runtimes (Docker, rkt et al.)

- Lightweight compute node operating systems/VMMs

- Optimizations of virtual machine monitor platforms, hypervisors

- QoS and SLA in hypervisors and network virtualization

- Cloud based network and system management for SDN and NFV

- Management, deployment and monitoring of virtualized environments

- Virtual per job / on-demand clusters and cloud bursting

- Performance measurement, modelling and monitoring of virtualized/cloud workloads

- Programming models for virtualized environments

- Virtualization in data intensive computing and Big Data processing

- Cloud reliability, fault-tolerance, high-availability and security

- Heterogeneous virtualized environments, virtualized accelerators, GPUs and co-processors

- Optimized communication libraries/protocols in the cloud and for HPC in the cloud

- Topology management and optimization for distributed virtualized applications

- Adaptation of emerging HPC technologies (high performance networks, RDMA, etc..)

- I/O and storage virtualization, virtualization aware file systems

- Job scheduling/control/policy in virtualized environments

- Checkpointing and migration of VM-based large compute jobs

- Cloud frameworks and APIs

- Energy-efficient / power-aware virtualization

The Workshop on Virtualization in High­-Performance Cloud Computing (VHPC) aims to

bring together researchers and industrial practitioners facing the challenges

posed by virtualization in order to foster discussion, collaboration, mutual exchange

of knowledge and experience, enabling research to ultimately provide novel

solutions for virtualized computing systems of tomorrow.

The workshop will be one day in length, composed of 20 min paper presentations, each

followed by 10 min discussion sections, plus lightning talks that are limited to 5 minutes.

Presentations may be accompanied by interactive demonstrations.

Important Dates

February 29, 2016 - Lightning talk abstract registration

March 21, 2016 - Paper/publishing track abstract registration

April 25, 2016 - Full paper submission

May 30, 2016 Acceptance notification

June 23, 2016 - Workshop Day

July 25, 2016 - Camera-ready version due

Chair

Michael Alexander (chair), TU Wien, Austria

Anastassios Nanos (co-chair), NTUA, Greece

Balazs Gerofi (co-chair), RIKEN Advanced Institute for Computational Science, Japan

Program committee

Stergios Anastasiadis, University of Ioannina, Greece

Costas Bekas, IBM Research, Switzerland

Jakob Blomer, CERN

Ron Brightwell, Sandia National Laboratories, USA

Roberto Canonico, University of Napoli Federico II, Italy

Julian Chesterfield, OnApp, UK

Stephen Crago, USC ISI, USA

Christoffer Dall, Columbia University, USA

Patrick Dreher, MIT, USA

Robert Futrick, Cycle Computing, USA

Robert Gardner, University of Chicago, USA

William Gardner, University of Guelph, Canada

Wolfgang Gentzsch, UberCloud, USA

Kyle Hale, Northwestern University, USA

Marcus Hardt, Karlsruhe Institute of Technology, Germany

Romeo Kinzler, IBM, Switzerland

Brian Kocoloski, University of Pittsburgh, USA

Kornilios Kourtis, IBM Research, Switzerland

Nectarios Koziris, National Technical University of Athens, Greece

John Lange, University of Pittsburgh, USA

Nikos Parlavantzas, IRISA, France

Kevin Pedretti, Sandia National Laboratories, USA

Che-Rung Roger Lee, National Tsing Hua University, Taiwan

Giuseppe Lettieri, University of Pisa, Italy

Qing Liu, Oak Ridge National Laboratory, USA

Paul Mundt, Adaptant, Germany

Amer Qouneh, University of Florida, USA

Carlos Reaño, Technical University of Valencia, Spain

Seetharami Seelam, IBM Research, USA

Josh Simons, VMWare, USA

Borja Sotomayor, University of Chicago, USA

Dieter Suess, TU Wien, Austria

Craig Stewart, Indiana University, USA

Anata Tiwari, San Diego Supercomputer Center, USA

Kurt Tutschku, Blekinge Institute of Technology, Sweden

Amit Vadudevan, Carnegie Mellon University, USA

Yasuhiro Watashiba, Osaka University, Japan

Nicholas Wright, Lawrence Berkeley National Laboratory, USA

Chao-Tung Yang, Tunghai University, Taiwan

Gianluigi Zanetti, CRS4, Italy

Paper Submission-Publication

Papers submitted to the workshop will be reviewed by at least two

members of the program committee and external reviewers. Submissions

should include abstract, key words, the e-mail address of the

corresponding author, and must not exceed 10 pages, including tables

and figures at a main font size no smaller than 11 point. Submission

of a paper should be regarded as a commitment that, should the paper

be accepted, at least one of the authors will register and attend the

conference to present the work.

The format must be according to the Springer LNCS Style. Initial

submissions are in PDF; authors of accepted papers will be requested

to provide source files.

Format Guidelines:

ftp://ftp.springer.de/pub/tex/latex/llncs/latex2e/llncs2e.zip

Abstract, Paper Submission Link:

https://edas.info/newPaper.php?c=21801

Lightning Talks

Lightning Talks are non-paper track, synoptical in nature and are strictly limited to 5 minutes.

They can be used to gain early feedback on ongoing research, for demonstrations, to

present research results, early research ideas, perspectives and positions of interest to the

community. Submit abstract via the main submission link.

General Information

The workshop is one day in length and will be held in conjunction with the International

Supercomputing Conference - High Performance (ISC) 2016, June 19-23, Frankfurt, Germany.

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Deadline Extension: Graph Algorithm Building Blocks (GABB) Workshop

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We are extending the submission deadline by one week, upon requests. This is the only extension we will be able to give. 

Graph Algorithm Building Blocks (GABB) 2016
An IEEE IPDPS 2016 Workshop, May 23, 2016, Chicago, Illinois, USA

=== Scope and Goals ===

The Basic Linear Algebra Subprograms, introduced over 30 years ago, had a transformative effect on software for linear algebra. With the BLAS, researchers spend less time mapping algorithms onto specific features of hardware platforms and more time on interesting new algorithms.

Would it be practical to define an analogous set of basic building blocks for graph algorithms?  Can we define a core set of mathematical primitives from which we can build most (if not all) important graph algorithms? If we can agree on the mathematical foundations, how would these interact with the data structures used in graph algorithms and result in an API the graph algorithms research community could support?

These questions will be the topic for the second “Graph Algorithms Building Blocks” workshop.  Our goal is an interactive workshop where the full range of issues behind “Graph Algorithms Building Blocks” will be explored.   We want an interactive “workshop” so papers that report preliminary results and unproven but interesting ideas will also be considered.

=== Submission and Dates ===

Submitted manuscripts may not exceed ten (10) single-spaced double-column pages using 10-point size font on 8.5x11-inch pages (IEEE conference style), including figures, tables, and references (see IPDPS Call for Papers for more details). Papers shorter than 10 pages are welcome. All papers will be peer-reviewed. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.

Important dates: 

paper submissions due Jan 29, 2016 EST Midnight (updated)

author notification: Feb 12, 2016 (updated)

camera-ready due Feb 26, 2016.

- Workshop web page: http://graphanalysis.org/workshop2016.html

- Submission page (EDAS): http://edas.info/newPaper.php?c=21807.

=== Program Committee ===

Tim Mattson, Intel Corp. (Chair)

David A. Bader, Georgia Institute of Technology

Jonathan Berry, Sandia National Labs

Aydın Buluç, Lawrence Berkeley National Lab

John Gilbert, UC Santa Barbara

Jeremy Kepner, MIT Lincoln  Labs

Chris Long, US Department of Defense

Kamesh Madduri, Penn State University

Henning Meyerhenke, Karlsruhe Institute of Technology
John Owens, University of California, Davis
Fabrizio Petrini, IBM
Sivan Toledo, Tel-Aviv University

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CFP: Deadline Extension for LSPP 2016

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-----------------------------------------------------------------

Call for papers:      Workshop on LARGE-SCALE PARALLEL PROCESSING

               to be held in conjunction with

IEEE International Parallel and Distributed Processing Symposium

                     Chicago, Illinois, USA

                      May 27th, 2016

**NEW** SUBMISSION DEADLINE:  January 28th, 2016

-----------------------------------------------------------------

The workshop on Large-Scale Parallel Processing is a forum that 

focuses on computer systems that utilize thousands of processors 

and beyond. Large-scale systems, referred to by some as 

extreme-scale and Ultra-scale, have many important research 

aspects that need detailed examination in order for their 

effective design, deployment, and utilization to take place. 

These include handling the substantial increase in multi-core 

on a chip, the ensuing interconnection hierarchy, communication, 

and synchronization mechanisms. Increasingly this is becoming an 

issue of co-design involving performance, power and reliability 

aspects. The workshop aims to bring together researchers from 

different communities working on challenging problems in this 

area for a dynamic exchange of ideas. Work at early stages of 

development as well as work that has been demonstrated in 

practice is equally welcome.

Of particular interest are papers that identify and analyze novel

ideas rather than providing incremental advances in the following

areas: 

- LARGE-SCALE SYSTEMS : exploiting parallelism at large-scale,

  the coordination of large numbers of processing elements,

  synchronization and communication at large-scale, programming

  models and productivity

- NOVEL ARCHITECTURES AND EXPERIMENTAL SYSTEMS : the design of

  novel systems, the use of processors in memory (PIMS),

  parallelism in emerging technologies, future trends.

- MULTI-CORE : utilization of increased parallelism on a single

  chip (MPP on a chip such as the Cell and GPUs), the possible

  integration of these into large-scale systems, and dealing with

  the resulting hierarchical connectivity.

- MONITORING, ANALYSIS AND MODELING : tools and techniques for 

  gathering performance, power, thermal, reliability, and other 

  data from existing large scale systems, analyzing such data 

  offline or in real time for system tuning, and modeling of 

  similar factors in projected system installations.

- ENERGY MANAGEMENT: Techniques, strategies, and experiences 

  relating to the energy management and optimization of 

  large-scale systems.

- APPLICATIONS : novel algorithmic and application methods,

  experiences in the design and use of applications that scale to

  large-scales, overcoming of limitations, performance analysis

  and insights gained.

- WAREHOUSE COMPUTING: dealing with the issues in advanced 

  datacenters that are increasingly moving from co-locating many 

  servers to having a large number of servers working cohesively, 

  impact of both software and hardware designs and optimizations 

  to achieve best cost-performance efficiency. 

Results of both theoretical and practical significance will be 

considered, as well as work that has demonstrated impact at 

small-scale that will also affect large-scale systems. Work may 

involve algorithms, languages, various types of models, or 

hardware.

-----------------------------------------------------------------

SUBMISSION GUIDELINES

Papers should not exceed eight single-space pages (including 

figures, tables and references) using a 10-point font on 8.5x11

inch pages. Submissions in PostScript or PDF should be made 

using EDAS (www.edas.info). Informal enquiries can be made to 

Kevin.Barker@pnnl.gov. Submissions will be judged on correctness,

originality, technical strength, significance, presentation

quality and appropriateness. Submitted papers should not have

appeared in or under consideration for another venue.

IMPORTANT DATES

Submission deadline:  January 28th  2016 ** Extended **

Notification of acceptance:  February 14th  2016

Camera-Ready Papers due:  February 26th  2016

-----------------------------------------------------------------

WORKSHOP CHAIRS

Kevin J. Barker               Pacific Northwest National Laboratory, USA

Eric Van Hensbergen       ARM, USA

Chris Carothers               Rensselaer Polytechnic Institute, USA

PROGRAM COMMITTEE

Pavan Balaji            Argonne National Laboratory, USA

Laura Carrington        San Diego Supercomputer Center, USA

I-Hsin Chung            IBM T.J. Watson Research Lab, USA

Tim German              Los Alamos National Laboratory, USA

Georg Hager             University of Erlangen, Germany

Simon Hammond           Sandia National Laboratory, USA

Martin Herbordt         Boston University, USA

Daniel Katz             University of Chicago, USA

Celso Mendes            University of Illinois Urbana-Champagne

Phil Roth               Oak Ridge National Laboratory, USA

Jose Sancho             Barcelona Supercomputer Center, USA

Gerhard Wellein         University of Erlangen, Germany

Ulrike Yang             Lawrence Livermore National Laboratory

Workshop Webpage: http://hpc.pnl.gov/conf/LSPP/

__________________________________________

Kevin J. Barker

Modeling and Simulation Team Lead

High Performance Computing Group

Advanced Computing, Mathematics, and Data Division

Pacific Northwest National Laboratory

(509) 375-6743

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EuroMPI 2016 Call for Papers, Posters, and Tutorials

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***************************************************************************************
* EuroMPI 2016
* Call for papers, posters and tutorials
*
* Organised by EPCC at The University of Edinburgh, in cooperation with ACM SIGHPC.
* Edinburgh, Scotland, United Kingdom, 25-28 September 2016
*
* http://www.eurompi2016.ed.ac.uk
***************************************************************************************
(This call can be viewed online at: http://www.eurompi2016.ed.ac.uk/call-submissions)

Call for papers, posters and tutorials

The aim of this conference is to bring together all of the stakeholders involved in developments and applications related to the Message Passing Interface (MPI). As the pre-eminent meeting for users, developers and researchers to interact and discuss new developments and applications of message-passing parallel computing, the annual meeting has a long, rich tradition.

EuroMPI 2016 will continue to focus on benchmarks, tools, parallel I/O, fault tolerance, and parallel applications using MPI, enhancements and extensions to MPI, and alternative interfaces for high-performance homogeneous/heterogeneous/hybrid systems. Through the presentation of contributed papers, poster presentations and invited talks, attendees will have the opportunity to share ideas and experiences and to contribute to the improvement and furthering of message-passing and related parallel programming paradigms. In addition to the main conference’s technical program, one-day or half-day workshops will be held.

Topics of interest for the meeting include, but are not limited to:

• Shortcomings of MPI, alternatives to MPI and reasons for choosing not to use MPI for high-performance computing.
• MPI implementation issues and improvements, including extensions to MPI, towards Exascale computing, such as many-cores, GPGPU, and heterogeneous architectures.
• Hybrid and heterogeneous programming using MPI and interoperability with other interfaces.
• Interaction between message-passing software and hardware, in particular new high performance architectures.
• MPI support for data-intensive parallel applications.
• New MPI-IO mechanisms and I/O stack optimizations.
• Fault tolerance and error handling in message-passing implementations and systems.
• Performance evaluation for MPI and MPI based applications.
• Automatic performance tuning of MPI applications and implementations.
• Verification of message passing applications and protocols.
• Applications using message-passing, in particular in Computational Science and Scientific Computing.
• Parallel algorithms and scalable communication patterns in the message-passing paradigm.
• New programming paradigms implemented over MPI, like hierarchical programming and global address spaces.
• MPI parallel programming and application performance for cloud computing.

EuroMPI 2016 is now open to authors for submissions via easychair at:
https://easychair.org/conferences/?conf=eurompi2016

We are accepting submissions in the following categories:

• Full paper (minimum 5 pages, using ACM ICPS format): submission deadline 1st May 2016
• Short paper (maximum 4 pages, using ACM ICPS format): submission deadline 1st May 2016
• Poster (300-500 word abstract): submission deadline 1st May 2016
• White paper: submission deadline 15th June 2016
• Tutorial: submission deadline 8th April 2016

General Chair:
Jack Dongarra, University of Tennessee

Program Co-chairs:
• Daniel Holmes, EPCC, The University of Edinburgh
• Toni Collis, EPCC, The University of Edinburgh
• Mark Parsons, EPCC, The University of Edinburgh
• Jesper Träff, TUW, Vienna University of Technology

Tutorial/Workshop Chair:
• Lorna Smith, EPCC, The University of Edinburgh

Industry Chair:
• George Graham, EPCC, The University of Edinburgh

Program Committee:
• Rosa M. Badia, Barcelona Supercomputing Center
• Pavan Balaji, Argonne National Laboratory
• Puri Bangalore, UAB
• Ivy Bo Peng, KTH
• Ron Brightwell, Sandia National Laboratories
• Camille Coti, Laboratoire d'Informatique de Paris Nord
• Anthony Danalis, Innovative Computing Laboratory, University of Tennessee
• Christian Engelmann, Oak Ridge National Laboratory
• Ana Gainaru, Mellanox Technology
• Javier Garcia-Blas, Universidad Carlos III de Madrid
• Stéphane Génaud, ENSIIE, Université de Strasbourg
• Ganesh Gopalakrishnan, University of Utah
• Ryan Grant, Sandia National Laboratories
• William Gropp, University of Illinois at Urbana-Champaign
• Thomas Herault, Innovative Computing Laboratory, University of Tennessee
• Torsten Hoefler, ETH Zurich
• Florin Isaila, Universidad Carlos III de Madrid and Argonne National Laboratory
• Dries Kimpe, Argonne National Laboratory
• Alice Koniges, NERSC, LBNL
• Guillaume Mercier, INPB
• Kathryn Mohror, Lawrence Livermore National Laboratory
• Kengo Nakajima, The University of Tokyo
• Rolf Rabenseifner, HLRS, University of Stuttgart
• Martin Schulz, Lawrence Livermore National Laboratory
• David E. Singh, Universidad Carlos III de Madrid
• Jeff Squyres, Cisco Systems, Inc.
• Bronis de Supinski, Lawrence Livermore National Laboratory
• Frédéric Suter, CC IN2P3 / CNRS
• Guillermo L. Taboada, Torusware and Universidade da Coruna
• Denis Trystram, Grenoble Institute of Technology
• Keith Underwood, Intel Corporation
• Xin Yuan, Florida State University


EPCC, The Univesrity of Edinburgh
James Clerk Maxwell Building
Peter Guthrie Tait Road
Edinburgh
EH9 3FD
UK
Email: info@eurompi.ed.ac.uk
Tel:  +44 (0) 131 650 5030
Fax: +44 (0) 131 650 6555

--
Dan Holmes
Applications Consultant in HPC Research
EPCC, The University of Edinburgh
James Clerk Maxwell Building
The Kings Buildings
Peter Guthrie Tait Road
Edinburgh
EH9 3FD
T: +44(0)131 651 3465
E: dholmes@epcc.ed.ac.uk

*Please consider the environment before printing this email.*


The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.

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********************************************************************************

CFP: BeyondMR'16 - 3rd Workshop on Algorithms and Systems for MapReduce and Beyond

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* Call for papers *

BEYONDMR'16
3rd Workshop on Algorithms and Systems for MapReduce and Beyond, July 1, 2016.
https://sites.google.com/site/beyondmr2016/

Held in conjunction with SIGMOD 2016
San Francisco, USA, June 26th - July 1st, 2016
http://sigmod2016.org/

----------------
KEYNOTES
----------------

Author: Ion Stoica, AMPLab, University of California Berkeley

Title: Spark: Past, Present, and Future

Abstract: Almost six years ago we started the Spark project at UC Berkeley.
Spark is a cluster computing engine that is optimized for in-memory
processing, and unifies support for a variety of workloads, including
batch, interactive querying, streaming, and iterative computations. Spark
is now the most active big data project in the open source community, and
is already being used by over one thousand organizations. In this talk,
I'll take a look back at Spark's humble beginnings, discuss it's current
status, and the new and exciting developments that are coming up.

----------------
WORKSHOP FOCUS
----------------

The third BeyondMR workshop aims to explore algorithms, computational
models, architectures, languages and interfaces for systems that need
large-scale parallelization and systems designed to support efficient
parallelization and fault tolerance. These include specialized programming
and data-management systems based on MapReduce and extensions, graph
processing systems, data-intensive workflow and dataflow systems.

We invite submissions on topics such as

Frameworks for Large-Scale Analytical Processing:
- Models, architectures and languages for data processing pipelines,
data-intensive workflows, DAGs of operations/MapReduce jobs, dataflows,
and data-mashups.
- Extensions of MapReduce with more fundamental functions other than Map
and Reduce and more complex dataflow connections between function inputs
and outputs.
- Expressing and parallelising iterations, incremental iterations, and
programs consisting of large DAGs of operations.
- Approaches to achieving fault tolerance and to recovering from failures.

Algorithms for Large-Scale Data Processing:
- Methods and techniques for designing efficient algorithms for MapReduce
and similar systems.
- Experiments and experience with new algorithms in these settings.

Cost Models and Optimization Techniques:
- Formal definitions of models that evaluate the efficiency of algorithms
in large-scale parallel processing systems taking into account the
requirements of such systems in different applications.
- Testing and benchmarking of MapReduce extensions and data-intensive
workflows.

Resource Management for Many-Task Computing:
- Scheduling of tasks and load-balancing techniques.
- Methods to tackle data skewness.
- Study of cases where automatic data distribution in MapReduce and
similar systems does not provide sufficient data balancing.
- Design of algorithms that avoid skewness.
- Extensions of MapReduce that automatically tackle data skewness.

----------------
IMPORTANT DATES
----------------
Papers submission deadline:             Sun March 5, 2016
Authors notification:           Sun April 11, 2016
Deadline for camera-ready copy:         Sun May 1, 2016
Workshop:                               Fri July 1, 2016

----------------
SUBMISSION GUIDELINES
----------------
We invite full research or experience papers (up to 10 pages), or short
papers (up to 4 pages) describing research in progress, formatted using
the ACM double-column style
(http://conferences.sigcomm.org/imc/2009/sig-alternate-10pt.cls)

----------------
PUBLICATION
----------------
The workshop proceedings will be published in ACM DL and the organizers will prepare a SIGMOD Record report.

---------------------------
ORGANIZERS
---------------------------
Foto Afrati     (National Technical University of Athens, Greece)
Jan Hidders     (TU Delft, The Netherlands)
Christopher Re  (Stanford, USA)
Jacek Sroka     (University of Warsaw, Poland)
Jeffrey Ullman  (Stanford University)

---------------------------
Program Committee (in progress)
---------------------------

– Chris Re,                     Stanford University (PC chair)
– Foto Afrati,                  National Technical University of Athens
– Jeffrey Ullman,               Stanford University
– Jacek Sroka,                  University of Warsaw
– Jan Hidders,                  Delft University of Technology
– Zhengkui Wang,                Singapore Institute of Technology
– Khalid Belhajjame,            PSL, Universite Paris-Dauphine, LAMSADE
– Sourav Bhowmick,              Nanyang Technological University
– Graham Cormode,               University of Warwick
– Asterios Katsifodimos,        Technical University of Berlin
– Paris Koutris,                University of Washington
– Dionysios Logothetis,         Facebook
– Frank McSherry,               ETH Zurich
– Krzysztof Onak,               IBM Research
– Mark Santcroos,               Rutgers University
– Gautam Shroff,                Tata Consultancy Services RD
– Dan Suciu,                    University of Washington
– Jianwu Wang,                  University of Maryland, Baltimore County
– Tim Kraska,                   Brown University
– Krzysztof Rzadca,             University of Warsaw
– Semih Salihoglu,              Stanford University
- Ulf Leser                     Humboldt-Universität zu Berlin
- Fabio Porto                   National Laboratory of Scientific Computation, Brasil
- Eiko Yoneki                   University of Cambridge
- Umut Acar                     Carnegie Mellon University
- Daniel De Oliveira            Fluminense Federal University
- Tamer Özsu                    University of Waterloo
- Anthony Tung                  National University of Singapore
- Sergei Vassilvitskii          Google
- Yogesh Simmhan                Indian Institute of Science, Bangalore

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FINAL DEADLINE EXTENSION AsHES 2016 Workshop Co-located with IPDPS

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===========================================================

AsHES 2016 - CALL FOR PAPERS
===========================================================

The Sixth International Workshop on Accelerators and Hybrid Exascale Systems (AsHES)
http://www.mcs.anl.gov/events/workshops/ashes/2016
May 23rd, 2016

To be held in conjunction with
30th IEEE International Parallel and Distributed Processing Symposium
Chicago Hyatt Regency, Chicago, Illinois, USA

Important Dates (AoE)
========================================

Paper Submission: Jan. 20, 2016 (FINAL EXTENSION)
Paper Notification: Feb. 18, 2016
Camera-Ready: Feb. 25, 2016

Workshop Scope and Goals
========================================

Current and emerging systems are deployed with heterogeneous architectures and accelerators
of more than one type (e.g. GPGPU, Intel® Xeon Phi(tm), FPGA) along with hybrid processors of
both lightweight and heavyweight cores (e.g APU, big.LITTLE). Such architectures also comprise
hybrid memory systems equipped with stacked/hierarchical memory and non-volatile memory in
addition to regular DRAM. Programming such a system can be a real challenge along with locality,
scheduling, load balancing, concurrency and so on.

This workshop focuses on understanding the implications of accelerators and heterogeneous
designs on the hardware systems, porting applications, performing compiler optimizations, and
developing programming environments for current and emerging systems. It seeks to ground
accelerator research through studies of application kernels or whole applications on such
systems, as well as tools and libraries that improve the performance and productivity of
applications on these systems.

The goal of this workshop is to bring together researchers and practitioners who are involved in
application studies for accelerators and other heterogeneous systems, to learn the opportunities
and challenges in future design trends for HPC applications and systems.


Topics of interest for workshop submissions include (but are not limited to):

  * Strategies for programming heterogeneous systems using high-level models such as
    OpenMP, OpenACC, low-level models such as OpenCL, CUDA;
  * Methods and tools to tackle challenges in scientific computing at extreme scale;
  * Strategies for application behavior characterization and performance optimization for
    accelerators;
  * Techniques for optimizing kernels for execution on GPGPU, Intel® Xeon Phi™, and future
    heterogeneous platforms;
  * Models of application performance on heterogeneous and accelerated HPC systems;
  * Compiler Optimizations and tuning heterogeneous systems including parallelization, loop
    transformation, locality optimizations, Vectorization;
  * Implications of workload characterization in heterogeneous and accelerated architecture
    design;
  * Benchmarking and performance evaluation for accelerators;
  * Tools and techniques to address both performance and correctness to assist application
    development for accelerators and heterogeneous processors;
  * System software techniques to abstract application domain-specific functionalities for
    accelerators;

Papers Submission Guidelines
========================================

Papers should present original research and should provide sufficient background material to
make them accessible to the broader community.

Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point
size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references.
See the style templates for latex or word for details.

Submissions will be judged based on relevance, significance, originality, correctness and clarity.

Submission site: https://easychair.org/conferences/?conf=ashes2016

Journal Special Issue
========================================

The best papers of AsHES 2016 will be included in a Special Issue on Topics on Heterogeneous
Computing of the Elsevier International Journal on Parallel Computing (PARCO), edited by Sunita
Chandrasekaran and Antonio J. Peña. This special issue is dedicated for the papers accepted in
the AsHES workshop. The submission to this special issue is by invitation only.

Steering Committee
========================================

Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, University of Houston, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, IBM, Canada

General Chair
========================================

James Dinan, Intel Corporation

Program Chair and Co-Chairs
========================================

Wenguang Chen, Tsinghua University, China
Sunita Chandrasekaran, University of Delaware, USA
Antonio J. Peña, Barcelona Supercomputing Center, Spain

Program Committee
========================================

Sangmin Seo, Argonne National Laboratory, USA
Piotr Luszczek, University of Tennessee Knoxville, USA
Anthony Danalis, University of Tennessee, USA
Gabriele Jost, Intel Corporation, USA
Jeff Hammond, Intel Labs, USA
Seeyong Lee, Oak Ridge National Laboratories, USA
John Lidel, Texas Tech University, USA
James Beyer, NVIDIA Corporation, USA
Kamesh Madduri, The Pennsylvania State University, USA
Mahantesh M Halappanavar, Pacific Northwest National Laboratory, USA
Stephen Olivier, Sandia Nationl Lab, USA
Guido Juckeland, TU Dresden, Germany
Matthias Muller, TU Aachen, Germany
Barry Rountree, Lawrence Livermore National Laboratory, USA
Hennry Jin, NASA, USA
Dong Li, University of Calfornia, Merced, USA
Khaled Hamidouche, The Ohio State University, USA
Huimin Cui, Institute of Computing Technology, CAS
Xipeng Shen, North Carolina State University, USA
Bronis de Supinski, Lawrence Livermore National Laboratory, USA
Hao Wang, Virginia Tech, USA
Naoya Maruyama, RIKEN AICS
Siva Kumar Sastry Hari, NVIDIA Corporation, USA
Guangyu Sun, Peking University, China
Sriram Krishnamoorthy, Pacific Northwest National Laboratory, USA
Nacho Navarro, UPC- Univesity Politecnica de Catalunya, Spain
Kelly Shaw, University of Richmond, USA
Yongpeng Zhang, Stone Ridge Technology, USA
Fangfang Xia, Argonne National Laboratory, USA

Questions?
========================================

Please send any queries about the AsHES workshop to ashes@mcs.anl.gov

-- 
Antonio J. Peña, PhD
Senior Researcher
Barcelona Supercomputing Center
http://www.bsc.es/about-bsc/staff-directory/pena-antonio

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CFP - PSTI 2016: Sixth International Workshop on Parallel Software, Tools and Tool Infrastructures

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===============================================================================

                              CALL FOR PAPERS

              Sixth International Workshop on Parallel Software
                  Tools and Tool Infrastructures (PSTI 2016)
                            Philadelphia, PA, USA

                    Held in Conjunction with ICPP 2016,
           The 45th International Conference on Parallel Processing

                  Philadelphia, PA, USA, August 16-19, 2016

                       http://www.psti-workshop.org

===============================================================================

BACKGROUND

The advent of multicore and manycore systems requires that programmers
understand how to design, write and debug parallel programs
effectively.  The increased complexity of multi-threaded parallel
programming on multicore platforms requires more insight into program
behavior, and necessitates the use of tools that can support
programmers in migrating existing software to multicore platforms, and
in writing new multi-threaded parallel software.  Programmers need
increasingly sophisticated methods for instrumentation, measurement,
analysis and modeling of applications.  Developers need both
sophisticated tools to support parallel software development, and an
extensible tool infrastructure that promotes integration of existing
and new tools, and simplifies information exchange and access.


KEY DATES

Submission Deadline:         April 8, 2016
Notification of Acceptance:  May 9, 2016
Final Papers Due:            June 3, 2016
Workshop Date:               Aug 16, 2016


TOPICS

Topics of interest include, but are not limited to

 * Static and dynamic analysis tools
 * Instrumentation, measurement, analysis, and modeling of applications
 * Analysis and visualization tools for assisting programmers with
   parallel software design
 * Active testing tools
 * Applications profiling and performance analysis
 * Data visualization and analysis infrastructures


PAPER SUBMISSION

Submissions should be formatted according to the CPS standard
double-column format with a font size of 10 pt or larger and are
strictly limited to 10 pages in length. Submissions should represent
original, substantive research results. At least one author of every
accepted paper is required to attend the conference in order for the
paper to be included in the final proceedings. Proceedings of the
workshop will be published in electronic format and will be available
at the conference.

For paper submissions please use

  https://www.easychair.org/conferences/?conf=psti2016


For more details please see the PSTI website at

  http://www.psti-workshop.org/2016


WORKSHOP ORGANIZERS

Josef Weidendorfer, TU Munich, Germany
Karen L. Karavanic, Portland State University, USA
Karl Fuerlinger, LMU Munich, Germany



PROGRAM COMMITTEE

Xavi Aguilar, KTH Stockholm, Sweden
Daniel Becker, Siemens AG, Germany
Karl Fuerlinger, University of Munich, Germany
Sascha Hunold, TU Wien, Austria
Ali Jannesari, TU Darmstadt, Germany
Karen Karavanic, Portland State University, USA
Andreas Knuepfer, TU Dresden, Germany
Alice Koniges, Lawrence Berkeley National Laboratory, USA
Jialin Liu, Lawrence Berkeley National Laboratory, USA
Nathan Tallent, Pacific Northwest National Laboratory, USA
Josef Weidendorfer, Technische Universitaet Muenchen, Germany
Brian Wylie, FZ Juelich, Germany

===============================================================================
--
Dr. Josef Weidendorfer, Informatik, Technische Universität München
TUM I-10 - FMI 01.04.035 - Tel. 089 / 289-18454
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