Tuesday 31 January 2017

HiCOMB 2017 extended submission deadline

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HiCOMB 2017, 16th IEEE International Workshop on High Performance Computational Biology
 Monday, May 29, 2017, Buena Vista Palace Hotel, Orlando, FL, USA
The submission deadlines have been extended by two weeks!  
 Call For Papers
 The size and complexity of genome- and proteome-scale data sets in bioinformatics continues to grow at a furious pace, and the analysis of these complex, noisy, data sets demands efficient algorithms and high performance computer architectures. Hence high-performance computing has become an integral part of research and development in bioinformatics, computational biology, and medical and health informatics. The goal of this workshop is to provide a forum for discussion of latest research in developing high-performance computing solutions to data- and compute-intensive problems arising from all areas of computational life sciences. We are especially interested in parallel and distributed algorithms, memory-efficient algorithms, large scale data mining techniques including approaches for big data and cloud computing, algorithms on multicores, many-cores and GPUs, and design of high-performance software and hardware for biological applications.
 The workshop will feature contributed papers as well as invited talks from reputed researchers in the field.
 Topics of interest include but are not limited to:
·       Bioinformatics data analytics;     Biological network analysis;   Cloud-enabled solutions for computational biology;   Computational genomics and metagenomics;   Computational proteomics and metaproteomics; DNA assembly, clustering, and mapping;  Energy-aware high performance biological applications;     Gene identification and annotation; High performance algorithms for computational systems biology; High throughput, high dimensional data analysis: flow cytometry and related proteomic data; Parallel algorithms for biological sequence analysis;   Molecular evolution and phylogenetic reconstruction algorithms;  Protein structure prediction and modeling;  Parallel algorithms in chemical genetics and chemical informatics;    Transcriptome analysis with RNASeq
 Details and Important Dates
 To submit a paper, please upload a PDF file through Easy Chair at the URL https://easychair.org/conferences/?conf=hicomb2017. Submitted manuscripts may not exceed ten (10) single-spaced double-column pages using a 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references (see IPDPS Call for Papers for more details). All papers will be reviewed. Proceedings of the workshops will be distributed at the conference and are submitted for inclusion in the IEEE Explore Digital Library after the conference.
 Workshop submissions due:     February 13, 2017
Author notification:    February 27, 2017
Final Camera-ready papers due: March 22, 2017 
Workshop:  May 29, 2017
Workshop Organizers
 Alex Pothen and Ananth Grama 
Department of Computer Science, Purdue University
------------------






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Second Annual Workshop on Emerging Parallel and Distributed Runtime Systems and Middleware (IPDRM17) Deadline extension: February 5th, 2017

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                                          IPDRM 2017
                  Second Annual Workshop on Emerging Parallel and Distributed                        
                                  Runtime Systems and Middleware
                                              June 2, 2017
                                         Orlando, Florida, USA.

Held in conjunction with the 31st IEEE International Parallel and Distributed Processing Symposium, (IEEE IPDPS 2017), 
                        May 29-June 2, 2017, Orlando, Florida, USA.


Submission deadlines: January 29th, 2017 EXTENDED February 5th, 2017

Overview
------------

Node architectures of extreme-scale systems are rapidly increasing in complexity. Emerging homogeneous and heterogeneous designs provide massive multi-level parallelism, but developing efficient runtime systems and middleware that allow applications to efficiently and productively exploit these architectures is extremely challenging. Moreover, current state-of-the-art approaches may become unworkable once energy consumption, resilience, and data movement constraints are added. The goal of this workshop is to attract the international research community to share new and bold ideas that will address the challenges of design, implementation, deployment, and evaluation of future runtime systems and middleware.

Topics
--------

This workshop will emphasize novel, disruptive research ideas over incremental advances. We will solicit papers on topics including, but not limited to, the following areas:

Runtime System/Middleware Design, Evaluation and Usage
====================================

* Runtime/Middleware for emerging HPC and cloud computing platforms
* Runtime/Middleware for Big Data Computing
* Modeling and Performance Analysis of Runtime Systems
* Comparison studies of different runtime systems and middleware
* Tuning and Optimization studies
* Interactions between Runtime Systems and Middleware
* Runtime-architecture co-design

Constraints and Issues for Runtime Systems and Middleware
=====================================

* Energy- and Power-aware schemes
* Fault Tolerance and Reliability
* Scalable high-performance I/O and access to Big Data
* Memory management
* Runtime data analysis (e.g., in-situ analysis)
* Real-time solutions and QOS
* Virtualization, provisioning, and scheduling
* Scalability of novel runtime systems and applications using them

Design Principles and Programming Support
===========================

* High-level programming models (e.g., thread and task based models, data parallel models, and stream programming) and domain-specific languages
* Programming frameworks, parallel programming, and design methodologies
* Methodologies and tools for runtime and middleware design, implementation , verification, and evaluation
* Wild and crazy ideas on future Runtime System and Middleware

Submissions
-----------

We invite two kinds of submissions to this workshop: (1) Full-length research papers (8-page limit); (2) Short papers (4-page limit), which can take the form of position papers, experience reports, or surveys/comparisons of runtime systems and middleware. Papers should not exceed eight (or four) single-spaced pages (including figures, tables and references) using 10-point font on 8.5x11-inch pages. Submissions will be judged on correctness, originality, technical strength, significance, presentation quality, and appropriateness. Submitted papers should not have appeared in or under consideration for another venue. A full peer-review process will be followed with each paper being reviewed by at least 3 members of the program committee.

Submissions should follow the IEEE Conference Proceedings templates found at http://www.ieee.org/conferences_events/conferences/publishing/templates.html. Camera-ready copy will need to conform to IPDPS guidelines; these will be announced during author notification


Important Dates
---------------

Paper Submission: January 29th -- EXTENDED: February 5th
Paper Notification: February 22nd
Final Paper Due: March 7th


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The 13th International Workshop on High-Performance, Power-Aware Computing (HPPAC'17) Submission Deadline extended to February 5, 2017

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The 13th International Workshop on High-Performance, Power-Aware Computing (HPPAC'17)
Program co-chairs:   Shuaiwen Leon Song, Pacific Northwest National Lab
                                         Richard Vuduc, Georgia Tech
Publicity Chair:           Shirley Moore, Oak Ridge National Laboratory
                                          
Proceedings Chair:    Joseph Manzano, Pacific Northwest National Lab
Venue
To be held on Monday, May 29th, 2017, in conjunction with the 31st IEEE International Parallel and Distributed Symposium (IPDPS 2017).
Overview
Power and energy are now recognized as first-order constraints in high-performance computing.  Optimizing performance under power and energy bounds requires coordination across not only the software stack (compilers, operating and runtime systems, job schedulers) but also coordination with cooling systems and outwards to electrical suppliers.  As we continue to move towards exascale and extreme scale computing, understanding how power translates to performance becomes an increasingly critical problem.
The purpose of this workshop is to provide a forum where cutting-edge research in the above topic can be shared with others in the community. As such, while we welcome full (10 page) papers as in previous years, we are now also soliciting short papers (4 pages max).  While both should address power aware computing issues, short papers will be judged primarily on their interest to the community.  As such, these may be position papers, initial results, open problems, software announcements, or interesting work that does not reach the level of a full-paper treatment. All papers will be subject to single-blind peer review, and the quality of
both the short and standard papers is expected to be high.
Topics of particular interest include (but are not limited to):
* Performance optimization under node, job, cluster and site power bounds
* Power/performance tradeoffs across accelerators, processors and DRAM
* Cooling/performance tradeoffs
* Translating budgetary bounds into power and energy bounds.
* Power-efficient system design, from computer center to silicon
* Effects of compiler optimizations on application power and energy efficiency
* Power- and energy-aware job schedulers, runtime systems and operating systems
* Models of power and performance, from processors and components to computer centers
* Evaluations of hardware power and energy controls
Submission Guidelines
We invite two kinds of submissions to this workshop: (1) Full-length research papers (10-page limit); (2) Short papers (4-page limit), which can take the form of position papers, experience reports, or power and energy characterizations of current systems. Papers should not exceed ten (or four) single-spaced pages (including figures, tables and references) using 12-point font on 81⁄2x11-inch pages. Submissions will be judged on correctness, originality, technical strength, significance, presentation quality, and relevance. Submitted papers should not have appeared in or be under consideration for another venue. A full peer-review process will be followed with each paper being reviewed by at least three members of the program committee.
Submissions should follow the IEEE Conference Proceedings templates found at http://www.ieee.org/conferences_events/conferences/publishing/templates.html Camera-ready copy will need to conform to IPDPS guidelines; these will be announced during author notification.
Important dates
Paper Submission: January 29th, 2017 EXTENDED February 5th, 2017
Paper Notification: February 22nd, 2017
Final Paper Due: March 7th, 2017
Program Committee
-              Dongyoon Lee, Virginia Tech, USA       
-              Torsten Wilde, Leibniz Supercomputing Centre, Germany
-              Jee Choi, IBM, USA
-              Ryan Friese, Pacific Northwest National Laboratory, USA
-              Kevin Barker, Pacific Northwest National Laboratory, USA
-              Thomas Ilsche, Technische Universitat Dresden, Germany
-              Koji Inoue, Kyushu University, Japan
-              Suzanne Rivoire, Sonoma State University, USA
-              Michael Bader, Institut für Informatik, Technische Universität München, Germany
-              Natalie Bates, Energy Efficient HPC Working Group, USA
-              Sunita Chandrasekaran, University of Delaware, USA
-              Lizhong Chen, Oregon State University, USA
-              Joseph Greathouse, AMD, USA
-              Matthias Maiterth, Ludwig Maximilians Universitat Munchen, Germany
-              Aniruddha Marathe, University of Arizona, USA
-              Shirley Moore, Oak Ridge National Laboratory, USA
-              Barry Rountree, Lawrence Livermore National Laboratory, USA
-              Bo Wang, RWTH Aachen University, Germany

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Monday 30 January 2017

submission deadline extension for BeyondMR 2017

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Due to several requests, and because of the uncertainty concerning the time and place of SIGMOD 2017, the submission deadline for BeyondMR 2017 has been extended with 3 weeks to:

- Friday 17 February, 2017.

Below you find the updated CFP.


* Call for papers *

BEYONDMR'17
The 4th Workshop on Algorithms and Systems for MapReduce and Beyond, May 19, 2017.
https://sites.google.com/site/beyondmr2017/

Held in conjunction with SIGMOD 2017
(Location to be announced) May 14-19, 2017
http://sigmod2017.org/

----------------
 KEYNOTES
----------------

Author: Ke Yi, Hong Kong University of Science and Technology, China

Title: The relationships among coarse-grained parallel models

----------------
 WORKSHOP FOCUS
----------------

The third BeyondMR workshop aims to explore algorithms, computational
models, architectures, languages and interfaces for systems that need
large-scale parallelization and systems designed to support efficient
parallelization and fault tolerance. These include specialized programming
and data-management systems based on MapReduce and extensions, graph
processing systems, data-intensive workflow and dataflow systems.

We invite submissions on topics such as:

Frameworks for Large-Scale Analytical Processing:
- Models, architectures and languages for data processing pipelines,
  data-intensive workflows, networks of operations/MapReduce jobs, dataflows,
  and data-mashups.
- Analysis of programs for workflow systems, e.g., Spark.
- Expressing and parallelising iterations, incremental iterations, and
  programs consisting of large networks of operations.
- Approaches to achieving fault tolerance and to recovering from failures.

Algorithms for Large-Scale Data Processing:
- Methods and techniques for designing efficient algorithms for MapReduce
  and similar systems.
- Experiments and experience with new algorithms in these settings.

Cost Models and Optimization Techniques:
- Formal definitions of models that evaluate the efficiency of algorithms
  in large-scale parallel processing systems taking into account the
  requirements of such systems in different applications.
- Testing and benchmarking of MapReduce extensions and data-intensive
  workflows.

Resource Management for Many-Task Computing:
- Scheduling of tasks and load-balancing techniques.
- Study of cases where automatic data distribution in MapReduce and
  similar systems does not provide sufficient data balancing.
- Algorithms, methods and frameworks to address data skewness.

----------------
IMPORTANT DATES
----------------
Papers submission deadline:             Fri Feb 17, 2017
Authors notification:                   Sun March 19, 2017
Deadline for camera-ready copy:         Sun March 26, 2017
Workshop:                               Fri May 19, 2017

----------------
SUBMISSION GUIDELINES
----------------
We invite full research or experience papers (up to 10 pages), or short
papers (up to 4 pages) describing research in progress, formatted using
the ACM double-column style
(http://conferences.sigcomm.org/imc/2009/sig-alternate-10pt.cls)

----------------
PUBLICATION
----------------
The workshop proceedings will be published in ACM DL and the organizers
will prepare a SIGMOD Record report.

---------------------------
ORGANIZERS
---------------------------
- Foto Afrati                   National Technical University of Athens, Greece)
- Jan Hidders                   Vrije Universiteit Brussel, Belgium
- Paris Koutris                 University of Wisconsin-Madison, USA
- Jacek Sroka                   University of Warsaw, Poland
- Jeffrey Ullman                Stanford University

---------------------------
Program Committee
---------------------------

- Paris Koutris,                University of Wisconsin-Madison (CHAIR)
- Foto Afrati,                  National Technical University of Athens
- Sourav S. Bhowmick,           Nanyang Technological University
- Yingyi Bu,                    Couchbase
- Ahmed Eldawy,                 University of California, Riverside
- Todd Green,                   LogicBlox
- Jan Hidders,                  Vrije Universiteit Brussel
- Asterios Katsifodimos,        Technical University of Berlin
- Paraschos Koutris,            University of Wisconsin-Madison
- Nectarios Koziris,            National Technical University of Athens
- Ulf Leser,                    Humboldt-Universität zu Berlin
- Dionysios Logothetis,         Facebook
- Frank McSherry
- Frank Neven,                  Hasselt University
- Daniel de Oliveira,           Fluminense Federal University
- Krzysztof Onak,               IBM T.J. Watson Research Center
- Fabio Porto,                  National Laboratory of Scientific Computation
- Chris Re,                     Stanford University
- Krzysztof Rzadca,             University of Warsaw
- Semih Salihoglu,              University of Waterloo
- Mark Santcroos,               Rutgers University
- Francesco Silvestri,          IT University of Copenhagen
- Yogesh Simmhan,               Indian Institute of Science, Bangalore
- Jacek Sroka,                  University of Warsaw
- Dan Suciu,                    University of Washington
- Jeffrey Ullman,               Stanford University
- Theodore Vassilakis,          Microsoft
- Jianwu Wang,                  University of Maryland, Baltimore County
- Zhengkui Wang,                National University of Singapore
- Ke Yi,                        Hong Kong University of Science and Technology
- Eiko Yoneki,                  University of Cambridge
- Matei Zaharia,                Stanford University

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Fw: [Deadline January 31] RAW 2017 - 24th Reconfigurable Architectures Workshop

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__________________________________________________________________

                  CALL FOR PAPERS
__________________________________________________________________

     24th Reconfigurable Architectures Workshop
                                     RAW 2017            
Buena Vista Palace Hotel         
Orlando, Florida, USA, May 29-30 2017
__________________________________________________________________

QUICK LINK:       Web site: http://raw.necst.it/

IMPORTANT DATES:
                New Submission deadline: January 31, 2017
                Decision notification February 17, 2017

__________________________________________________________________
__________________________________________________________________

The 24th Reconfigurable Architectures Workshop (RAW 2017) will be held in Orlando, Florida USA in May 2017. RAW 2017 is associated with the 31st Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2017) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand.
The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing.
The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

__________

SUBMISSION OF PAPERS

All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. Manuscript for full paper should be not exceed 8 single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages (IEEE conference style) including references, figures and tables. Manuscript for short papers should be not exceed 4 single-space, double-column pages.
Papers are to be submitted through EasyChair. Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. It is also expected that all accepted papers (regular or short) will be presented at the workshop by one of the authors.
All papers must be submitted electronically in PDF format.Submissions can be made through:
* the RAW2017 web site: http://raw.necst.it/

___________

IMPORTANT DATES
                New submission deadline: January 31, 2017
                Decision notification February 17, 2017
                Conference: May 29-30, 2017

___________

KEYNOTES
“Heterogeneous Technology Configurable Fabrics: Leveraging Reconfiguration as a Pathway Towards Emerging Devices”
Ronald F. DeMara, University of Central Florida

“Elastic Dataflow Engines for the Masses”
Georgi Gaydadjiev - VP of Dataflow Software Engineering of Maxeler Technologies
___________

TOPICS OF INTEREST

    Hot Topics in Reconfigurable Computing
                Configurable Cloud
                Heterogeneous Computing in Data Centers
                Accelerating Data Center Workloads
                FPGA-based Deep Learning
                Accelerating Genomic Computations
                Acceleration of Data Analytics
               Reconfigurable Computing in the IoT era
                Organic Computing, Biology-Inspired Solutions
                Applications in Finance

    Architectures & CAD
                Algorithmic Techniques and Mapping
                Emerging Technologies (optical models, 3D Interconnects, devices)
                Reconfigurable Accelerators
                Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)
                FPGA-based MPSoC and Multicore
                Distributed Systems & Networks
                Wireless and Mobile Systems
                Critical issues (Security, Energy efficiency, Fault-Tolerance)

    Runtime & System Management
                Run-Time Reconfiguration Models and Architectures
                Autonomic computing systems
                Operating Systems and High-Level Synthesis
                High-Level Design Methods (Hardware/Software co-design, Compilers)
                System Support (Soft processor programming)
                Runtime Support
                Reconfiguration Techniques
                Simulations and Prototyping (performance analysis, verification tools)

___________

ORGANIZERS

Workshop Chairs
                Marco D. Santambrogio, Politecnico di Milano, Italy
                Ramachandran Vaidyanathan, Louisiana State University, USA

Program Chairs
                Diana Goehringer, Ruhr-University Bochum, Germany
                Donatella Sciuto, Politecnico di Milano, Italy

Program Vice Chairs
                Dirk Stroobandt, Ghent University, Belgium
                Francesca Palumbo, Università di Sassari, Italy
                Ann Gordon-Ross, University of Florida, USA

Steering Committee
                Juergen Becker, Karlsruhe Insttute of Technology, Germany
                Viktor K. Prasanna, University of Southern California, USA
                Ramachandran Vaidyanathan, Louisiana State University, USA

Publicity
                Brian Veale, IBM, USA
                Ivan Beretta, University of Westminster, UK


The University of Westminster is a charity and a company limited by guarantee. Registration number: 977818 England. Registered Office: 309 Regent Street, London W1B 2UW.
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Friday 27 January 2017

[CFP] DEADLINE EXTENDED: CF'17 - ACM International Conference on Computing Frontiers 2017

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==================================================================
 ACM International Conference on Computing Frontiers 2017 (CF'17)
                May 15 - 17, 2017, Siena, Italy

                         CALL FOR PAPERS

                   www.computingfrontiers.org
==================================================================


  EXTENDED SUBMISSION DEADLINE


The next ACM International Conference on Computing Frontiers will be
held May 15-17 in Siena, Italy. Computing Frontiers is an eclectic,
collaborative community of researchers who investigate emerging
technologies in the broad field of computing: our common goal is to
drive the scientific breakthroughs that transform society. Technology
is experiencing revolutions in memory devices and systems, networks,
electronic device production, machine learning, data analytics, cloud
computing, techniques to improve power and energy efficiency, systems
portability/wearability, to name but a few areas. New application
domains that affect everyday life are emerging, especially in this era
of highly interconnected and collaborative cyber-physical systems.
Boundaries between the state-of-the-art and revolutionary innovation
constitute the frontiers that mark the advances of science,
engineering, and information technology.

Early research that envisions future technologies provides the bases
that allow novel materials, devices, and systems to become mainstream.
Collaborative efforts among researchers with different expertises and
backgrounds enables revolutionary scientific breakthroughs that lead
to innovative solutions over a wide spectrum of computer systems, from
embedded and hand-held/wearable devices to supercomputers and data
centers.



IMPORTANT DATES
===============

Submissions deadline:   February 3, 2017
Notification:           March 14, 2017
Camera-Copy Papers Due: April 4, 2017
Conference Dates:       May 15 - 17, 2017


TOPICS OF INTEREST
==================

We seek original research contributions at the frontiers of a wide
range of topics, including novel computing paradigms, computational
models, algorithms, application paradigms, development environments,
compilers, operating environments, computer architecture, hardware
substrates, memory technologies, and smarter life applications:

* Algorithms and Models of Computing -- Approximate and inexact
  computing, quantum and probabilistic computing

* Biological Computing Models -- Brain computing, neural computing,
  computational neuroscience, biologically-inspired architectures
  Limits on Technology Scaling and Moore's Law -- Defect- and
  variability-tolerant designs, graphene and other novel materials,
  nanoscale design, optoelectronics, dark silicon

* Uses of Technology Scaling -- 3D stacked technology, challenges of
  many-core designs, accelerators, PCM's, novel memory architectures,
  mobile devices

* Embedded and Cyber-Physical Systems -- Design space exploration,
  modeling and development frameworks for interconnected systems and CPS
  and CPSoS, ultra-low power designs, energy scavenging, reactive and
  real-time systems, reconfigurable and self-aware systems, sensor
  networks and internet of things, and architectural innovation for
  wearable computing

* Big Data Analytics -- High performance data analytics, data search and
  representation, architecture, and system design

* Machine and Deep Learning -- innovative algorithms and architectures,
  neuromorphic approaches

* Large-Scale System Design -- Homogeneous and heterogeneous
  architectures, runtimes, networking technologies and protocols, power-
  and energy-management for cloud and grid systems, data centers,
  exa-scale computing

* Compiler Technologies -- Advanced/novel analyses,
  hardware/software integrated solutions, domain-specific languages,
  high-level synthesis

* Security -- Methods, system support, and hardware for protecting
  against malicious code; real-time implementations of security
  algorithms and protocols; quantum and post-quantum cryptography;
  advanced persistent threats, cyber and physical attacks, and
  countermeasures

* Computers and Society -- Education, health, cost/energy-efficient
  design, smart cities, and emerging markets

* Interdisciplinary Applications -- Applications bridging multiple
  disciplines in interesting ways

We also strongly encourage submissions in emerging fields that may not
fit into traditional categories -- if in doubt, please contact the PC
co-chairs by email.


CONFERENCE WEBSITE
==================

http://www.computingfrontiers.org/


WORKSHOPS
=========

We are pleased to host the following co-located workshops:

  * Big Data Analytics (BigDAW '17)
    Organized by Roberta Piscitelli (EGI)
    and Giovanni Mariani (IBM Research).

  * Design of Low Power Embedded Systems (LP-EMS '17)
    Organized by Francesco Conti (ETH Zurich),
    Paolo Meloni (University of Cagliari) and Daniel Menard (INSA Rennes).

  * Malicious Software and Hardware in the Internet of Things (MAL-IoT '17)
    Organized by Georg Becker (Ruhr University of Bochum)
    and Francesco Regazzoni (Catholic University of Louvain).


SUBMISSION
==========

Submission website: https://easychair.org/conferences/?conf=cf17

Authors are invited to submit full papers, position papers, trend
papers, and poster abstracts to the main conference.

Papers must be submitted through the conference submission website.
Authors must declare in advance to which category they are submitting.

Full papers are a maximum of eight (8) double-column pages in ACM
conference format. Authors may purchase up to two (2) additional pages
at 100 Euro per page. Authors can submit full papers of up to 10
double-column pages, provided that they agree to pay for the
additional pages if the paper is accepted. All other types of
submissions should be at least two (2) pages and not more than four
(4) pages in the same format. These limits include figures, tables,
and references. Our review process is double-blind: please remove all
identifying information from the paper submission (and cite your own
work in the third person). Authors of interesting work not mature
enough for an oral presentation may be offered the option of
presenting their work as posters.

Position papers, trend papers, poster abstracts and workshop papers
will be published in the proceedings and in the ACM Digital Library.
As per ACM guidelines, at least one unique author of each accepted
paper is required to register for the conference.

Selected papers from the Computing Frontiers 2017 conference will be
invited to extend their work for publication in a special issue of the
Springer Journal of Signal Processing Systems (JSPS).


ORGANIZATION
============

Computing Frontiers 2017 Chairs

General Chair:        Roberto Giorgi, University of Siena, IT
Program Co-Chairs:    Michela Becchi, North Carolina State University, US
                      Francesca Palumbo, University of Sassari, IT
Workshops Co-Chair:   John Feo, PNNL, US
Industry/Sponsorship Chair:
                      Antonino Tumeo, PNNL, US
Poster Chair:         Miquel Moreto, Barcelona Supercomputing Center, ES
Finance Chair:        Peter Zinterhof, University of Salzburg, AT
Registration Chair:   Gianluca Palermo, Politecnico di Milano, IT
Local Arrangements Chair:
                      Monica Bianchini, University of Siena, IT
Publicity Chairs:     Maurizio Palesi, KORE University, IT
                      Yuhui Deng, Jinan University, CN
Submission Chair:     Magnus Sjalander,
                      Norwegian University of Science and Technology, NO
Publications Chair:   Carlo Galuzzi, Maastricht University, NL
Web Chair:            Kristian Rietveld, Leiden University, NL

Computing Frontiers Steering Committee

    Monica Alderighi, INAF, IT
    John Feo, PNNL, US
    Hubertus Franke, New York University / IBM Research, US
    Georgi Gaydadjiev, Maxeler, GB
    Alexander Heinecke, Intel Parallel Computing Lab, US
    Paul Kelly, Imperial College London, GB
    Sally A. McKee, Chalmers University of Technology, SE
    Claudia Di Napoli, ICAR-CNR, IT
    Gianluca Palermo, Politechnico di Milano, IT
    Francesca Palumbo, University of Sassari, IT
    Kristian Rietveld, Leiden University, NL
    Valentina Salapura, IBM, US
    Pedro Trancoso, University of Cyprus, CY
    Carsten Trinitis, Technische Universitaet Muenchen, DE
    Antonino Tumeo, PNNL, US
    Josef Weidendorfer, Technische Universitaet Muenchen, DE 

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[CFP][Final Deadline Extension Jan 27th] SCRAMBL@CCGrid 2017: 3rd International Workshop on Scalable Computing For Real-Time Big Data Applications

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**** CALL FOR PAPERS ****


                               SCRAMBL'17: 
      The 3rd International Workshop on Scalable Computing 
              For Real-Time Big Data Applications

                held in conjunction with CCGrid'17:
      The 7th IEEE/ACM International Symposium on Cluster, 
                   Cloud and Grid Computing

                 Madrin, Spain - May 14-17, 2017            

SCRAMBL is a dedicated workshop to present and discuss leading
research results, use cases, innovative ideas, challenges, and
opportunities that arise from adopting real-time big data analytics at
large scale.  System-level researchers and practitioners active in the
area of high performance computing, cloud computing and distributed
systems in general will have an opportunity to understand what
patterns, use cases and challenges arise at application level in the
context of real-time big data analytics, which is of consequence in
the design of the infrastructure and runtime systems. In turn,
application-level researchers will have an opportunity to learn more
about new low-level technologies and runtime system that facilitate
easier design of algorithms, workflows and parallelization. Finally,
an another important category are the use case providers, be they
industrial, government or academia, which will have the opportunity to
learn about the options and feasibility of implementing their desired
real-time big data analytics solution in practice.

SCRAMBL, now at it's third edition is organized in conjunction with
CCGrid, which has traveled the world over, and this year will be held
in May in Madrid, Spain, for the first time.  Madrid is the capital of
Spain and gathers a thrilling mix of antique and modern cultures that
is reflected in their environment, monuments, and warm people.

== IMPORTANT DATES ==

Paper submission deadline: 27 January 2017
Paper notification due: 10 February 2017
List of accepted papers due: 14 February 2017
Camera ready papers: 1 March 2017

== SUBMISSIONS ==

Papers should be submitted through Easychair by selecting the relevant
track (3rd International Workshop on Scalable Computing For Real-Time
Big Data Applications) in the overall CCGrid submission system:

We welcome submissions in the form of: 
  * Outrageous ideas (up to 2 pages) 
  * Position papers (short papers up to 6 pages) 
  * Real-world use cases papers (up to 10 pages) 
  * Research papers (up to 10 pages) 

Papers must be formatted according to the 2-column IEEE format used by
They will be part of the proceedings and will be submitted to IEEE
Xplore for publication and EI indexing.  Submitted papers must
represent original and unpublished work, that is not currently under
review. All manuscripts will be evaluated according to their
significance, originality, technical content, style, clarity, quality
of presentation, and relevance to the workshop.  At least one author
of each accepted paper is expected to attend the workshop.

== TOPICS ==

Submissions relevant to the following topic are welcome:

Scalable models for near real-time cloud based processing
  * Data representation and data structures
  * Dynamic/temporal data
  * Heterogeneous data
  * Relational and linked Data
  * Semantic integration
  * Complex event processing
  * Messaging and data flow
  * Wokflows/processes
  * Scalable algorithms & architectures for real-time cloud based processing

Data extraction, cleaning, processing
  * Machine learning
  * Reasoning
  * Scalable architectures: Grids, Clouds, HPC, Clusters
  * Programming paradigms (e.g. MapReduce)
  * Big Data placement, scheduling and optimization
  * Real-time Big Data applications and use cases

Big Data in-use and challenges
  * Big Data mining and analytics
  * Big Data visualization and interactive mining

== ORGANIZATION ==

Co-chairs:

Charalampos Chelmis, University at Albany, USA 
Marc Frincu, West University of Timisoara, Romania 
Bogdan Nicolae, Huawei European Research Center, Germany

Program Committee:

Teodora Sandra Buda, IBM, Ireland
Shadi Ibrahim, INRIA, France
Florin Pop, Polytechnic University Bucharest, Romania
Radu Prodan, University of Innsbruck, Austria
Romain Rouvoy, Universite Lille 1 and INRIA, France
Jose Vazquez-Poletti, Universidad Complutense de Madrid, Spain
Yinglong Xia, Huawei Research America, USA
Vladimir Vlassov, KTH Royal Institute of Technology, Sweden
Gabriel Antoniu, INRIA, France
Alexandru Uta, Vrije Universiteit Amsterdam, Netherlands

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MICRO-50 Call For Papers

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MICRO-50 Call For Papers

Important dates

Abstracts due          March 28th, 2017
Papers due             April 4th, 2017
Response period        June 1st - June 14th, 2017
Author notification    July 5th, 2017

Webpage: https://www.microarch.org/micro50/
News: Twitter @MicroArchConf

The International Symposium on Microarchitecture (MICRO) is
the premier forum for the presentation and discussion of new
ideas in microarchitecture, compilers, hardware/software
interfaces, and design of advanced computing and communication
systems. The goal of MICRO is to bring together researchers
in the fields of microarchitecture, compilers, and systems
for technical exchange. The MICRO community has enjoyed
having close interaction between academic researchers and
industrial designers---we aim to continue and strengthen
this longstanding tradition at the 50th MICRO in
Boston, Massachusetts.

We invite original paper submissions related to
(but not limited to) the following topics:
* Processor, memory, interconnect, and storage architectures.
* Hardware, software, and hybrid techniques for improving
  system performance, energy-efficiency, cost, complexity,
  predictability, quality of service, reliability,
  dependability, security, scalability, programmer
  productivity, etc.
* Architectures for instruction-level, thread-level,
  and memory-level parallelism: superscalar, VLIW,
  data-parallel, multithreaded, multicore, manycore, etc.
* Compiler and microarchitectural techniques for
  parallelism (ILP, TLP, MLP).
* Low-power, high-performance, and cost/complexity-efficient
  architectures.
* Architectures for emerging platforms, including
  smartphones, cloud/datacenter, etc.
* Architectures and compilers for embedded processors,
  DSPs, GPUs, ASIPs (network processors, multimedia,
  wireless, deep learning, neuromorphic, etc.).
* Advanced software/hardware speculation and prediction schemes.
* Microarchitecture techniques to better support system
  software, programming languages, programmability, and compilation.
* Microarchitecture modeling and simulation methodology.
* Insightful experimental and comparative evaluation and
  analysis of existing microarchitectures, hardware/software
  mechanisms and workloads.

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Sunday 22 January 2017

iWAPT2017 (conjuction with IPDPS2017) - Final Deadline extended to Jan 31

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==============================================================
:: iWAPT 2017 :: CALL FOR PAPERS
The 12th International Workshop on Automatic Performance Tuning
http://www.iwapt.org/2017/

June 2, 2017 at Buena Vista Palace Hotel, Orlando, Florida, USA

The iWAPT 2017 will be held in conjunction with IPDPS 2017.
http://www.ipdps.org/
===============================================================

# Important dates

Submission closes: Tuesday, Jan 31, 2017 (AOE) **Extended**
Author notification: Friday, Feb 24, 2017
Camera-ready: Friday, March 10, 2017
Workshop: Friday, June 2, 2017

Submission site:
https://easychair.org/conferences/?conf=iwapt2017
(If you do not have an EasyChair account, please create it first.)

# About iWAPT

iWAPT (International Workshop on Automatic Performance Tuning) is a series of workshops that focus on research and techniques that address performance sustainability issues. It provides an opportunity for researchers and users of automatic performance tuning (AT) technologies to exchange ideas and experiences while applying such technologies to improve the performance of algorithms, libraries, and applications; in particular, on cutting edge computing platforms. The full-day workshops consist of invited keynote speaker presentations and 30-minute presentations of well-founded papers. Occasionally, exploratory papers are also accepted. Topics of interest include performance modeling, adaptive algorithms, autotuned numerical algorithms, libraries and scientific applications, empirical compilation, automated code generation, frameworks and theories of AT and software optimization, autonomic computing, and context-aware computing.

We are particularly interested in autotuning and its relationship to the
following areas (the list is not exhaustive):

* Machine-adaptive algorithms and software
* Program generation
* Performance analysis and modeling
* Parallel and distributed computing
* Numerical algorithms and libraries
* Multi- and manycore systems, heterogeneous architectures
* Compilation, e.g., iterative and empirical compilers
* Programming models
* Runtime systems
* Empirical search heuristics
* Power- and/or energy-aware computing

# Paper Submission guidelines

Submitted manuscripts may not exceed ten (10) single-spaced
double-column pages using 10-point size font on 8.5x11 inch pages
(IEEE conference style), including figures, tables, and references.
See style templates for details:

LaTex Package (ZIP):
http://www.ipdps.org/templates/IEEECS_CPS_LaTeX_Letter_2Col.zip

Word Template (ZIP):
http://www.ipdps.org/templates/IEEECS_CPS_8.5x11x2.zip

Files should be submitted by following the instructions available at the EasyChair portal (http://www.easychair.org/conferences/?conf=iwapt2017). Authors must ensure that electronically submitted files are formatted in PDF format for 8.5x11 inch paper.

Accepted submissions will be included in the IPDPS proceedings.

Submission implies the willingness of at least one of the authors to register and present the paper. The authors may use PDF eXpress, the IEEE’s online file converter and validation tool, to complete the final paper submission process. More details about camera-ready will also be announced when notification of the paper.



# Program Committee

PC Chair:  Toshiyuki Imamura, Riken AICS, Japan
PC Vice Chair: Jakub Kurzak, University of Tennessee, USA
Ray-Bing Chen, National Cheng Kung University, Taiwan
I-Hsin Chung, IBM T. J. Watson Research Center, USA
Björn Franke, University of Edinburgh, UK
Takeshi Fukaya, Hokkaido University, Japan
Michael Gerndt, Technische Universitaet Muenchen, Germany
Torsten Hoefler, ETH Zurich, Switzerland
Jeremy Johnson, Drexel University, USA
Takahiro Katagiri, Nagoya University, Japan
Che-Rung Lee, National Tsing Hua University, Taiwan
Osni Marques, Lawrence Berkeley National Laboratory, USA
Boyana Norris, University of Oregon, USA
Satoshi Ohshima, The University of Tokyo, Japan
Louis-Noel Pouchet, Ohio State University, USA
Daisuke Takahashi, University of Tsukuba, Japan
Hiroyuki Takizawa, Tohoku University, Japan
Teruo Tanaka, Kogakuin University, Japan
Richard Vuduc, Georgia Institute of Technology, USA
Weichung Wang, National Taiwan University, Taiwan
Yusaku Yamamoto, The University of Electro-Communications, Japan


# Organizing Committee

* (General Chair) Osni Marques, LBNL, USA
* (General Vice-Chair) Reiji Suda, The University of Tokyo, Japan
* (SC liaison) Takahiro Katagiri, The University of Tokyo, Japan
* (Finance Chair) Yusaku Yamamoto, The University of Electro-Communications, Japan
* (Web Chair) Hisayasu Kuroda, Ehime University, Japan
* (Publicity Chair) Akihiro Fujii, Kogakuin University, Japan
* (PC Chair) Toshiyuki Imamura, RIKEN AICS, Japan

# Contact

iwapt2017@iwapt.org
===============================================================
iWAPT2017 Program Committee Chair
Dr. Toshiyuki Imamura
Advanced Institute for Computational Science, RIKEN
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